Abstract: A method and apparatus with flash memory control are provided. The method includes performing first programming on a target memory cell of a cell array while adjusting a first programming time and a programming voltage, when a cell current of the target memory cell is determined to satisfy a primary target in association with the first programming, performing second programming on the target memory cell while adjusting a second programming time, and when the cell current of the target memory cell is determined to satisfy a secondary target in association with the second programming, terminating programming on the target memory cell.

Abstract: A neural network accelerator including always-on circuitry configured to determine pre-processed data, buffer circuitry including a plurality of banks configured to store the determined pre-processed data, and processor circuitry including a neural network model and configured to perform power-gating, the neural network model being configured to perform a neural network computation on the pre-processed data.

Abstract: A device including a memory array including N+1 resistive memory cells, the N+1 resistive memory cells including resistor values representing an N-bit sequence, the resistor values being determined based on a stuck resistor value of an error memory cell on a wordline including the error memory cell, the resistor values being set respectively and a write encoder configured to generate N+1 write signals respectively indicative of the resistor values to be set for the N+1 resistive memory cells, and N is an integer greater than or equal to 1.

Abstract: An in-memory computing (IMC) macro has a mode alternating between a first mode and a second mode, and the IMC macro includes: an input control circuit configured to be capable of generating a signal in which a predefined pattern is applied to an input signal and of transmitting a previous operation result that is fed back, and which is performed depends on which mode the operating mode is in; a crossbar array including memory cells including an additional row that processes and stores the fed-back previous operation result, and columns including an adder tree corresponding to the memory cells; and a post arithmetic circuit configured to be capable of performing a first operation corresponding to a spiking neural network (SNN) and a second operation corresponding to an artificial neural network (ANN), wherein which of the first and second operations is performed depends on which mode is in effect.

Abstract: A multi-bit operation device includes a plurality of multi-bit cells, and a converter configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells, and each of the plurality of multi-bit cells comprises a memory configured to store a weight resistance corresponding to a multi-bit weight, a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance, a plurality of multiplexers connected to one another in parallel and connected to the memory in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input, a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance, a bit line con

Abstract: A light emitting display device includes a substrate, a plurality of anodes disposed on the substrate, a pixel defining layer having first openings overlapping each of the anodes, light emitting layers respectively disposed within the first openings of the pixel defining layer, a cathode formed on the light emitting layers and the pixel defining layer, an encapsulation layer disposed on the cathode, and a light blocking layer disposed on the encapsulation layer and including a second openings respectively overlapping the plurality of first openings. The first openings are formed in an elliptical shape. Among the first openings and the second openings, a first opening and a second opening corresponding to the first opening have different values in the major axis direction and the minor axis direction, which are the planar distances in the major axis direction and minor axis direction of the first opening in the plane.

Abstract: A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.

Abstract: The present invention relates to a cosmetic composition in which lipid fermentation metabolites are produced by fermenting vegetable oil with skin flora, and a method for producing the same. According to the present invention, lipid fermentation metabolites similar to skin lipids can be produced by fermenting vegetable oil with skin flora. Further, thereby, the skin affinity and skin barrier-protecting effect of the fermented vegetable oil can be maximized.

Abstract: A display device comprises a display panel, a panel support member disposed on a surface of the display panel and including segments that are spaced apart from each other, and a reflective layer disposed between the segments.

Abstract: A positive electrode for an all-solid-state battery includes a current collector, and a positive electrode active material layer on the current collector, the positive electrode active material layer including a positive electrode active material; a sulfide solid electrolyte; a dispersion medium including a compound of CH3C(?O)O—R1, where R1 is a C7 to C9 alkyl group; a binder; an electrolyte salt; one or more of a monofunctional or higher (meth)acrylate having an alkylene glycol group, an oligomer thereof; and a cross-linked product thereof, and a conductive material.

Abstract: There is provided a semiconductor device capable of improving performance and reliability of a device, by adjusting the arrangement of penetration patterns included in an electrode support for supporting the lower electrode. The semiconductor device includes a plurality of lower electrodes that are aligned with each other on a substrate along a first direction and a second direction different from the first direction, and a first electrode support that supports the lower electrodes, and includes a plurality of first penetration patterns, wherein the first electrode support includes a center region, and an edge region defined along a periphery of the center region, wherein the first penetration patterns include center penetration patterns that are spaced apart by a first interval in the center region, and wherein the first penetration patterns include edge penetration patterns that are spaced apart by a second interval different from the first interval in the edge region.

Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

Abstract: A display device may include a display panel which is flexible and includes a first surface on which an image is displayed and a second surface on which the image is not displayed, a connection film at least partially overlapping a side of the display panel in a plan view, a printed circuit board at least partially overlapping a side of the connection film in a plan view and electrically connected to the connection film, a control board spaced apart from the printed circuit board, and a cable electrically connecting the printed circuit board and the control board. The cable may have a spiral shape.

Abstract: A display device comprises a display panel, a panel support member disposed on a surface of the display panel and including segments that are spaced apart from each other, and a reflective layer disposed between the segments.

Abstract: There is provided a semiconductor device capable of improving performance and reliability of a device, by adjusting the arrangement of penetration patterns included in an electrode support for supporting the lower electrode. The semiconductor device includes a plurality of lower electrodes that are aligned with each other on a substrate along a first direction and a second direction different from the first direction, and a first electrode support that supports the lower electrodes, and includes a plurality of first penetration patterns, wherein the first electrode support includes a center region, and an edge region defined along a periphery of the center region, wherein the first penetration patterns include center penetration patterns that are spaced apart by a first interval in the center region, and wherein the first penetration patterns include edge penetration patterns that are spaced apart by a second interval different from the first interval in the edge region.

Abstract: A display device includes a base substrate; an outer bank on the base substrate and including an opening defining an emission area; a light-emitting element including at least an active layer and extending in a first direction in the emission area; a color mixing prevention member on the outer bank and having an opening defining a transmitting area; and a color control layer in the opening defined by the color mixing prevention member, wherein the transmitting area includes a first side at one side in the first direction and a second side at an opposite side in the first direction when viewed from top, and wherein a first distance between a first reference line and the first side of the transmitting area is equal to a second distance between the second side of the transmitting area and the first reference line.

Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

Abstract: A processor-implemented method includes receiving an input vector comprising a plurality of channels, performing a first convolution operation by allocating first chunks, obtained by dividing the input vector, to a plurality of first in-memory computing (IMC) macros, and performing a second convolution operation by allocating second chunks obtained by dividing a result of the first convolution operation to a plurality of second IMC macros.

Abstract: A convolutional neural network (CNN)-based analog in-sensor computing device may include a convolution layer including one or more convolution blocks configured to be used a predetermined number of times or more and perform a convolution operation, and an memory configured to temporarily store an output of the convolution layer and provide the stored analog output to a subsequent convolution layer.