Abstract: A means for correction for DC offset in an analog-to-digital converter which utilizes a hardware implemented iterative digital integration process. During the off time of an analog-to-digital converter thermal noise is digitized by the analog-to-digital converter and a specific number of least significant bits which are sufficient to handle the thermal noise levels are accumulated for a given number of samples. The accumulated sum of thermal noise samples is then converted into an analog signal and scaled by the number of samples taken so as to effectively find the average value from the sample collected. This scaled analog signal is then added to the thermal noise input signal wherein the process is repeated a predetermined number of times. Upon completion of the last iteration, the scaled analog signal which is representative of the DC offset inherent in the particular analog-to-digital converter is added to the true analog signal to be digitized.