Abstract: A dielectric waveguide interconnect system has a dielectric waveguide (DWG) a core surrounded by a cladding along the length of the DWG. One or more periodic structures are embedded along the length of the DWG such that the core of the DWG is integral to each of the one or more periodic structures.

Abstract: Signals on a dielectric waveguide are filtered to pass or block selected frequencies. A combined signal is received in the DWG, wherein the combined signal comprises at least a first frequency signal with a first wavelength and a second frequency signal with a second wavelength. The combined signal is split into a first portion and a second portion. The first portion of the combined signal is delayed by an amount of delay time to form a delayed first portion. The delayed first portion is joined with the received combined signal to form a filtered signal such that the first frequency signal is enhanced by constructive interference while the second frequency signal is diminished by destructive interference. A portion of the filtered signal is provided to a receiver, whereby the amplitude of the second frequency signal is attenuated in the filtered signal.

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and may have a cladding surrounding the dielectric core member. A radiated radio frequency (RF) signal may be received on a first portion of a radiating structure embedded in the end of a dielectric waveguide (DWG). Simultaneously, a derivative RF signal may be launched into the DWG from a second portion of the radiating structure embedded in the DWG.

Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.

Abstract: An encapsulated integrated circuit has transceiver circuitry operable to produce and/or receive a radio frequency (RF) signal, wherein bond pads on the IC die are coupled to the transceiver input/output (IO) circuitry. An antenna structure is coupled to the IO circuitry via the bond pads. Mold material encapsulates the IC die and the antenna structure, wherein the antenna structure is positioned so as to be approximately in alignment with a core of a dielectric waveguide positioned adjacent the encapsulated IC.

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and a transition region, with a cladding surrounding the dielectric core member. The body portion of the core member has a first dielectric constant. The transition region of the core member has a graduated dielectric constant value that gradually changes from the first dielectric constant value adjacent the body portion to a third dielectric constant.

Abstract: A digital system has a substrate having a top surface on which a waveguide is formed on the top surface of the substrate. The waveguide is formed by a conformal base layer formed on the top surface of the substrate, two spaced apart sidewalls, and a top conformal layer connected to the base layer to form a longitudinal core region. The waveguide may be a metallic or otherwise conductive waveguide, a dielectric waveguide, a micro-coax, etc.

Abstract: A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding.

Abstract: A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant value that is lower than the first dielectric constant value. A first port of a signal divider is connected to receive a signal from the DWG. A second port and a third port are each configured to output a portion of the signal received on the first port, wherein the first and second port are approximately in line and the third port is at an angle to a line formed by the first port and the second port. The first port and second port have a core member with the first dielectric constant value, and the third port has a core member with a second dielectric constant value that is higher than the first dielectric constant value.

Abstract: A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant value. A dielectric cladding surrounds the dielectric core member; the cladding has a second dielectric constant value that is lower than the first dielectric constant. A conductive shield layer surrounds a portion of the dielectric cladding.

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract: A rotatable coupler for dielectric wave guides is described. A first dielectric wave guide (DWG) has an interface surface at a one end of the DWG. A second DWG has a matching interface surface at an end of the second DWG. A rotatable coupling mechanism is coupled to the two DWG ends and is configured to hold the interface surface of the first DWG in axial alignment with the interface surface of the second DWG while allowing the interface surface of the first DWG to rotate axially with respect to the interface surface of the second DWG.

Abstract: A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.

Abstract: A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.

Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

Abstract: A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.