Abstract: A computing system may include a virtual cross metrology engine configured to construct a given virtual metrology model. The given virtual metrology model may take, as inputs, process parameters applied for the given step of a semiconductor fabrication process. The virtual cross metrology engine may also be configured to construct a subsequent virtual metrology model, and the subsequent step is performed after the given step in the semiconductor fabrication process. Doing so may include determining inputs for the subsequent virtual metrology model from a combination of the process parameters applied for the given step of the semiconductor fabrication process, process parameters applied for the subsequent step of the semiconductor fabrication process, and a wafer value for the given step of the semiconductor fabrication process that the given virtual metrology model is configured to predict.

Abstract: A computing system may include a virtual cross metrology engine configured to construct a given virtual metrology model. The given virtual metrology model may take, as inputs, process parameters applied for the given step of a semiconductor fabrication process. The virtual cross metrology engine may also be configured to construct a subsequent virtual metrology model, and the subsequent step is performed after the given step in the semiconductor fabrication process. Doing so may include determining inputs for the subsequent virtual metrology model from a combination of the process parameters applied for the given step of the semiconductor fabrication process, process parameters applied for the subsequent step of the semiconductor fabrication process, and a wafer value for the given step of the semiconductor fabrication process that the given virtual metrology model is configured to predict.

Abstract: Aspects of the disclosed technology relate to techniques of hotspot detection. Pinching-type hotspot candidates and bridging-type hotspot candidates are first identified in the layout design based on predetermined criteria. Simulation is then performed to derive aerial image intensity values for a plurality of sites on each of the pinching-type and bridging-type hotspot candidates. Pinching-type hotspots are determined from the pinching-type hotspot candidates based on one or more machine learning models for pinching-type hotspots, and bridging-type hotspots are determined from the bridging-type hotspot candidates based on one or more machine learning models for bridging-type hotspots. The input vector for the machine learning models is the aerial image intensity values for the plurality of sites.

Abstract: Aspects of the disclosed technology relate to techniques of hotspot detection. Pinching-type hotspot candidates and bridging-type hotspot candidates are first identified in the layout design based on predetermined criteria. Simulation is then performed to derive aerial image intensity values for a plurality of sites on each of the pinching-type and bridging-type hotspot candidates. Pinching-type hotspots are determined from the pinching-type hotspot candidates based on one or more machine learning models for pinching-type hotspots, and bridging-type hotspots are determined from the bridging-type hotspot candidates based on one or more machine learning models for bridging-type hotspots. The input vector for the machine learning models is the aerial image intensity values for the plurality of sites.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.

Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA(directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.

Abstract: Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design may be modified if one or more via-type feature groups in the via-type feature groups are non-DSA-compliant.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.

Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

Abstract: Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design may be modified if one or more via-type feature groups in the via-type feature groups are non-DSA-compliant.

Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.