Abstract: A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

Abstract: A PCI read access management system and method to manage read access between two agents providing PCI read requests to conduct contiguous read operations to a central resource at a PCI bus. Dual transaction control logic units are each respectively coupled to a separate one of the agents. An arbitration request connection couples the dual transaction control logic units. A PCI read request by one of the agents (e.g., agent A), and recognized by one of the dual transaction control logic units (e.g., unit 1), is signaled to the arbitration request connection, which arbitrates between the transaction control logic units for reserving the PCI bus for the one agent (agent A), and the one transaction control logic unit (unit 1) provides read access to the PCI bus for the one agent (agent A) for the contiguous read operations. The one transaction control logic unit (unit 1) then maintains the reservation until completion of the contiguous read operations.

Abstract: A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system.

Abstract: In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory.

Abstract: A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

Abstract: Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Abstract: To exchange a digital data input stream, a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to provide an output including the original digital data input stream. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the receiver. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.

Abstract: Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

Abstract: To exchange a digital data input stream, a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to provide an output including the original digital data input stream. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the receiver. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.

Abstract: A data storage system is described which allows data storage devices with different characteristics, such as differing data rates and transfer speeds, to be connected, and intermixed, along a single data and communication link. The data storage system comprises a storage controller, a first data storage device, a second data storage device, and a data and communication link coupled therebetween. The storage controller transfers data to and from the first data storage device using data locations within the data and communication link to transfer a data byte, a parity location to transfer the associated parity bit, and a communication signal location to transfer a data clocking signal. The storage controller further transfers data to and from the second data storage device using the data locations to transfer a data byte and the parity location to transfer a data clocking, or a data strobe, signal.

Abstract: A data transmission system includes a sender and a receiver, both employing different clock rates and a data bus coupled between the sender and the receiver for transmitting signals therebetween. The receiver generates an enable signal from the receiver clock to control data transmission at the sender. The enable signal is a pulse generated at each rising edge of the receiver clock and corresponds to the data transfer rate of the receiver clock. A detector module, located at the sender, receives and captures the asynchronous enable signal and initiates transmission of one data byte for each pulse of the enable signal, thereby automatically adjusting the data transfer rate of the sender to the data transfer rate of the receiver.

Abstract: A device controller is described within a data storage system for pre-fetching device work information from multiple data storage devices, and accumulating the device work information to immediately respond to a subsequent device poll command from a storage controller. The device controller includes a device receiver to receive the device poll command, a device transmitter to transmit a response to the device poll command, a device information register for storing the pre-fetched device work information for each data storage device, and a sequencer for periodically pre-fetching the device work information from each data storage device. The sequencer pre-fetches such information by verifying that no device subsystem command from the storage controller is pending in the device receiver, then issuing a background poll command to a selected device to query the device for its device work information, and storing the device work information in the device information register.

Abstract: The present invention reduces the delay in the completion of transferring data from a data channel to an input/output device and the time a host unit is released from performing the data transfer function. A time reduction is realized by monitoring the current data transfer between the data channel and a buffer device to establish a transfer rate. The transfer rate is used to anticipate and coordinate the transfer of the last bit of data from the data channel to coincide with the receipt of the data by the input/output (I/O) unit, effectively eliminating buffer device delay and allowing the host unit to be released from performing the data transfer. In the preferred embodiment, the transfer of the last bit of data by the data channel occurs at substantially the same time as the last bit of data is received by the I/O unit.

Abstract: A data transfer system providing parity uses a method and apparatus for transmitting a data clocking signal in a parity bit location along a data bus to latch an accompanying data byte at a receiving device. A transmitting device, coupled to the receiving device through the data bus, generates a data clock signal and latches the clock signal into the parity bit location of the data bus. The clock signal and data byte are then transmitted along the data bus to the receiving device. The receiving device uses the clock signal to latch the data byte from the data bus. Thus, the data transfer system uses the data clock signal transmitted in the parity bit location of the data bus to validate and synchronize the accompanying data byte at the receiving device.