Patents by Inventor Juan Buxo
Juan Buxo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6327182Abstract: A semiconductor device having a memory array includes memory cells (101-104), a word line (42), a first bit line (68), and a second bit line (76). Within the memory array, the first and second bit lines (68 and 76) lie at different elevations above the word line (42). Local interconnects (58) are electrically connected to the first bit line (68) and some of the current carrying electrodes (48) in the memory array. The local interconnects (58) allow offset connections to be made. For floating gate memory cells (101-104) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (46 and 48) of a memory cell (101) to be programmed without significantly disturbing data in adjacent floating gate memory cells (102-104).Type: GrantFiled: December 27, 1999Date of Patent: December 4, 2001Assignee: Motorola Inc.Inventors: Danny Pak-Chum Shum, Juan Buxo, John P. Hansen, Scott W. Krueger, James David Burnett, Eric Johan Salter
-
Patent number: 6101130Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).Type: GrantFiled: June 29, 1999Date of Patent: August 8, 2000Assignee: Motorola Inc.Inventors: Frank Kelsey Baker, Juan Buxo, Danny Pak-Chum Shum, Thomas Jew
-
Patent number: 5929478Abstract: A single level gate NVM device (20) includes a floating gate FET (11) and a capacitor (12) fabricated in two P-wells (27, 28) formed in an N-epitaxial layer (22) on a P-substrate (21). P+ sinkers (29, 31) and N-type buried layers (25, 26) provide isolation between the two P-wells (27, 28). The NVM device (20) is programmed or erased by biasing the FET (11) and the capacitor (12) to move charge carriers onto or away from a conductive layer (36) which serves as a floating gate (14) of the FET (11). Data is read from the NVM device (20) by sensing a current flowing in the FET (11) while applying a reading voltage to the capacitor (12).Type: GrantFiled: July 2, 1997Date of Patent: July 27, 1999Assignee: Motorola, Inc.Inventors: Patrice Michael Parris, Yee-Chaung See, Irenee M. Pages, Juan Buxo, Eric Scott Carman, Thierry Michel Sicard, Quang Xuan Nguyen
-
Patent number: 5892379Abstract: A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.Type: GrantFiled: June 2, 1997Date of Patent: April 6, 1999Assignee: Motorola, Inc.Inventors: Juan Buxo, Andreas A. Wild, Gary H. Loechelt, Thomas E. Zirkle, E. James Prendergast, Patrice M. Parris
-
Patent number: 5731612Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.Type: GrantFiled: April 28, 1997Date of Patent: March 24, 1998Assignee: Motorola, Inc.Inventors: Juan Buxo, Diann Dow, Vida Ilderem, Ziye Zhou, Thomas E. Zirkle
-
Patent number: 5541132Abstract: An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).Type: GrantFiled: March 21, 1995Date of Patent: July 30, 1996Assignee: Motorola, Inc.Inventors: Robert B. Davies, Vida Ilderem, Mark D. Griswold, Diann Dow, James E. Prendergast, Iksung Lim, Juan Buxo, Richard D. Sivan, James D. Burnett, Frank K. Baker
-
Patent number: 5510648Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.Type: GrantFiled: September 7, 1994Date of Patent: April 23, 1996Assignee: Motorola, Inc.Inventors: Robert B. Davies, Peter J. Zdebel, Juan Buxo
-
Patent number: 5372960Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.Type: GrantFiled: January 4, 1994Date of Patent: December 13, 1994Assignee: Motorola, Inc.Inventors: Robert B. Davies, Peter J. Zdebel, Juan Buxo