Abstract: Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended.

Abstract: A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

Abstract: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.

Abstract: A clone set of General Purpose Registers (GPRs) is created to be used by a set of helper thread binaries, which is created from a set of main thread binaries. When the set of main thread binaries enters a wait state, the set of helper thread binaries uses the clone set of GPRs to continue using unused execution units within a processor core. The set of helper threads are thus able to warm up local cache memory with data that will be needed when execution of the set of main thread binaries resumes.

Abstract: Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate.

Abstract: Processing system performance is improved while meeting power management constraints in a processing system by using activity factor headroom estimation. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.

Abstract: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. If executing a portion of the set of helper thread binaries results in the retrieval of data needed by the set of main thread binaries, then that retrieved data is utilized by the set of main thread binaries.

Abstract: A set of helper thread binaries is created from a set of main thread binaries. The helper thread monitors software or hardware ports for incoming data events. When the helper thread detects an incoming event, the helper thread asynchronously executes instructions that calculate incoming data needed by the main thread.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A system is provided for unified management of power, performance, and thermals in computer systems. This system incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The system employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The system provides interfaces for user-level interaction. The system also employs methods to address power/thermal concerns at multiple timescales. In addition, the system improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A method and system for improving processing performance by using activity factor headroom provides improved performance while meeting power management constraints in a processing system. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A method and system for providing performance estimations for a specified power budget provides an indication of the impact on processing performance when closed-loop power/performance control is employed to meet the specified power budget. A workload, which may be the actual workload, or a test workload is run to determine actual power consumption at intervals during the execution of the workload. The power values are examined and if they exceed the specified budget, which may be one of multiple possible budget values, an estimate of the amount by and duration for which the closed-loop power/performance control would have to reduce the performance of the system for each interval in order to provide an estimate of actual performance for the budgetary level(s). The estimate is informed by tests of the workload at each power/performance level to provide a non-linear estimate of the relationship between performance and power for the particular workload.