Patents by Inventor Juan Chacin
Juan Chacin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210398824Abstract: A substrate processing system includes an equipment front end module (EFEM) coupled to a vacuum-based mainframe, the EFEM including multiple interface openings. The system further includes a batch degas chamber attached to the EFEM at an interface opening of the multiple interface openings. The batch degas chamber includes a housing that is sealed to the interface opening of the EFEM. Within the housing is located a cassette configured to hold multiple substrates. A reactor chamber, attached to the housing, is to receive the cassette and perform an active degas process on the multiple substrates. The active degas process removes moisture and contaminants from surfaces of the multiple substrates. An exhaust line is attached to the reactor chamber to provide an exit for the moisture and contaminants.Type: ApplicationFiled: June 19, 2020Publication date: December 23, 2021Inventors: Dean C. Hruzek, Nir Merry, Marek Radko, Paul B. Reuter, Steven Sansoni, Sushant S. Koshti, John Joseph Mazzocco, Juan Chacin
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Patent number: 8852349Abstract: According to one aspect of the invention, an apparatus for reducing auto-doping of the front side of a substrate and reducing defects on the backside of the substrate during an epitaxial deposition process for forming an epitaxial layer on the front side of the substrate comprising: a means for forming a wafer gap region between the backside of the substrate and a susceptor plate, having an adjustable thickness; a means for ventilating auto-dopants out of the wafer gap region with a flow of inert gas, while inhibiting or prohibiting the flow of inert gas over the front side of the substrate; and a means for flowing reactant gases over the surface of the front side of the substrate, while inhibiting or prohibiting the flow of reactant gases near the surface of the backside of the substrate.Type: GrantFiled: September 15, 2006Date of Patent: October 7, 2014Assignee: Applied Materials, Inc.Inventors: Juan Chacin, Roger Anderson, Kailash Patalay, Craig Metzner
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Patent number: 8735772Abstract: Disclosed are laser scribing systems for laser scribing semiconductor substrates with backside coatings. In particular these laser scribing systems laser scribe opto-electric semiconductor wafers with reflective backside coatings so as to avoid damage to the opto-electric device while maintaining efficient manufacturing. In more particular these laser scribing systems employ ultrafast pulsed lasers at wavelength in the visible region and below in multiple passes to remove the backside coatings and scribe the wafer.Type: GrantFiled: February 20, 2011Date of Patent: May 27, 2014Assignee: Electro Scientific Industries, Inc.Inventors: Juan Chacin, Irving Chyr, Jonathan Halderman
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Publication number: 20130234149Abstract: A light emitting diode is made using a laser to texture the sidewalls of the bottom contact layer, without damaging a mesa. To do so, the substrate is mounted on a laser machining platform, and trenches are cut along lines through the semiconductor layer on the substrate using a first sequence of laser pulses having short pulse lengths that result in formation of textured sidewalls in the trenches, without causing recasting of the material. Then the substrate can be scribed along the lines of the trenches using a second sequence of laser pulses for singulation of die.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.Inventors: JONATHAN D. HALDERMAN, JUAN CHACIN, IRVING CHYR
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Patent number: 8372203Abstract: A film formation system 10 includes a processing chamber 15 bounded by sidewalls 18 and a top cover 11. In one embodiment, a susceptor 16 is rotatably disposed in the system 10, and overlaps with a first peripheral member 205 disposed around the sidewalls 18. A radiant heating system 313 is disposed under the susceptor 305 to heat the substrate 19. In another embodiment, the top cover 11 has equally spaced pyrometers 58 for measuring the temperature of the substrate 19 across a number of zones. The temperature of the substrate 19 is obtained from pyrometric data from the pyrometers 58.Type: GrantFiled: September 30, 2005Date of Patent: February 12, 2013Assignee: Applied Materials, Inc.Inventors: Juan Chacin, Aaron Hunter, Craig Metzner, Roger N. Anderson
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Publication number: 20120211477Abstract: Disclosed are laser scribing systems for laser scribing semiconductor substrates with backside coatings. In particular these laser scribing systems laser scribe opto-electric semiconductor wafers with reflective backside coatings so as to avoid damage to the opto-electric device while maintaining efficient manufacturing. In more particular these laser scribing systems employ ultrafast pulsed lasers at wavelength in the visible region and below in multiple passes to remove the backside coatings and scribe the wafer.Type: ApplicationFiled: February 20, 2011Publication date: August 23, 2012Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.Inventors: Juan Chacin, Irving Chyr, Jonathan Halderman
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Publication number: 20120175652Abstract: The present invention is a system and method for laser-assisted singulation of light emitting electronic devices manufactured on a substrate, having a processing surface and a depth extending from the processing surface. It includes providing a laser processing system having a picosecond laser having controllable parameters; controlling the laser parameters to form light pulses from the picosecond laser, to form a modified region having a depth which spans about 50% of the depth and substantially including the processing surface of the substrate and having a width less than about 5% of the region depth; and, singulating the substrate by applying mechanical stress to the substrate thereby cleaving the substrate into said light emitting electronic devices having sidewalls formed at least partially in cooperation with the linear modified regions.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.Inventors: Irving Chyr, Jonathan Halderman, Juan Chacin
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Patent number: 7700376Abstract: A retuning process particularly useful with an Ar/H2 smoothing anneal by rapid thermal processing (RTP) of a silicon-on-insulator (SOI) wafer performed after cleavage. The smoothing anneal or other process is optimized including a radial temperature profile accounting for the edge ring and exclusion zone and the vertically structured SOI stack or other wafer gross structure. The optimized smoothing conditions are used to oxidize a bare silicon wafer and a reference thickness profile obtained from it is archived. After extended processing of complexly patterned production wafers, another bare wafer is oxidized and its monitor profile is compared to the reference profile, and the production process is adjusted accordingly. In another aspect, a jet of cooling gas is preferentially directed to the edge ring and peripheral portions of the supported SOI wafer to cool them relative to the inner wafer portions.Type: GrantFiled: March 14, 2006Date of Patent: April 20, 2010Assignee: Applied Materials, Inc.Inventors: Juan Chacin, Sairaju Tallavajula, Sundar Ramamurthy
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Patent number: 7691204Abstract: A film formation system 10 has a processing chamber 15 bounded by sidewalls 18 and a top cover 11. In one embodiment, the top cover 11 has a reflective surface 13 for reflecting radiant energy back onto a substrate 19, pyrometers 405 for measuring the temperature of the substrate 19 across a number of zones, and at least one emissometer 410 for measuring the actual emissivity of the substrate 19. In another embodiment, a radiant heating system 313 is disposed under the substrate support 16. The temperature of the substrate 19 is obtained from pyrometric data from the pyrometers 405, and the emissometer 410.Type: GrantFiled: September 30, 2005Date of Patent: April 6, 2010Assignee: Applied Materials, Inc.Inventors: Juan Chacin, Aaron Hunter, Craig Metzner, Roger N. Anderson
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Publication number: 20080072820Abstract: The present invention provides methods and apparatus for processing semiconductor substrates. Particularly, the present invention provides a modular processing cell to be used in a cluster tool. The modular semiconductor processing cell of the present invention comprises a chamber having an inject cap, a gas panel module configured to supply one or more processing gas to the chamber through the inject cap, wherein the gas panel module is position adjacent the inject cap. The processing cell further comprises a lamp module positioned below the chamber. The lamp module comprises a plurality of vertically oriented lamps.Type: ApplicationFiled: June 25, 2007Publication date: March 27, 2008Inventors: Brian Burrows, Craig Metzner, Dennis Demars, Roger Anderson, Juan Chacin, David Carlson, David Ishikawa, Jeffrey Campbell, Richard Collins, Keith Magill, Imran Afzal
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Publication number: 20080069951Abstract: According to one aspect of the invention, an apparatus for reducing auto-doping of the front side of a substrate and reducing defects on the backside of the substrate during an epitaxial deposition process for forming an epitaxial layer on the front side of the substrate comprising: a means for forming a wafer gap region between the backside of the substrate and a susceptor plate, having an adjustable thickness; a means for ventilating auto-dopants out of the wafer gap region with a flow of inert gas, while inhibiting or prohibiting the flow of inert gas over the front side of the substrate; and a means for flowing reactant gases over the surface of the front side of the substrate, while inhibiting or prohibiting the flow of reactant gases near the surface of the backside of the substrate.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Inventors: Juan Chacin, Roger Anderson, Kailash Patalay, Craig Metzner
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Publication number: 20070077355Abstract: A film formation system 10 has a processing chamber 15 bounded by sidewalls 18 and a top cover 11. In one embodiment, the top cover 11 has a reflective surface 13 for reflecting radiant energy back onto a substrate 19, pyrometers 405 for measuring the temperature of the substrate 19 across a number of zones, and at least one emissometer 410 for measuring the actual emissivity of the substrate 19. In another embodiment, a radiant heating system 313 is disposed under the substrate support 16. The temperature of the substrate 19 is obtained from pyrometric data from the pyrometers 405, and the emissometer 410.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Juan Chacin, Aaron Hunter, Craig Metzner, Roger Anderson
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Publication number: 20070074665Abstract: A film formation system 10 includes a processing chamber 15 bounded by sidewalls 18 and a top cover 11. In one embodiment, a susceptor 16 is rotatably disposed in the system 10, and overlaps with a first peripheral member 205 disposed around the sidewalls 18. A radiant heating system 313 is disposed under the susceptor 305 to heat the substrate 19. In another embodiment, the top cover 11 has equally spaced pyrometers 58 for measuring the temperature of the substrate 19 across a number of zones. The temperature of the substrate 19 is obtained from pyrometric data from the pyrometers 58.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Juan Chacin, Aaron Hunter, Craig Metzner, Roger Anderson
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Publication number: 20060228818Abstract: A retuning process particularly useful with an Ar/H2 smoothing anneal by rapid thermal processing (RTP) of a silicon-on-insulator (SOI) wafer performed after cleavage. The smoothing anneal or other process is optimized including a radial temperature profile accounting for the edge ring and exclusion zone and the vertically structured SOI stack or other wafer gross structure. The optimized smoothing conditions are used to oxidize a bare silicon wafer and a reference thickness profile obtained from it is archived. After extended processing of complexly patterned production wafers, another bare wafer is oxidized and its monitor profile is compared to the reference profile, and the production process is adjusted accordingly. In another aspect, a jet of cooling gas is preferentially directed to the edge ring and peripheral portions of the supported SOI wafer to cool them relative to the inner wafer portions.Type: ApplicationFiled: March 14, 2006Publication date: October 12, 2006Applicant: Applied Materials, Inc.Inventors: Juan Chacin, Sairaju Tallavajula, Sundar Ramamurthy
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Patent number: 6916744Abstract: A method and apparatus for the formation of oxide in a manner having a planarizing effect on underlying material, e.g., silicon. In particular, an oxide having a nonuniform thickness profile is grown on the underlying material. The nonuniform thickness profile of the oxide is selected according to the nonuniform profile of the underlying material. Subsequent removal of the oxide leaves behind a planarized surface of the underlying material, as compared to the pre-oxidized surface.Type: GrantFiled: December 19, 2002Date of Patent: July 12, 2005Assignee: Applied Materials, Inc.Inventors: Vedapuram S. Achutharaman, Juan Chacin, Hali Forstner
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Publication number: 20040121598Abstract: A method and apparatus for the formation of oxide in a manner having a planarizing effect on underlying material, e.g., silicon. In particular, an oxide having a nonuniform thickness profile is grown on the underlying material. The nonuniform thickness profile of the oxide is selected according to the nonuniform profile of the underlying material. Subsequent removal of the oxide leaves behind a planarized surface of the underlying material, as compared to the pre-oxidized surface.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Applicant: Applied Materials, Inc.Inventors: Vedapuram S. Achutharaman, Juan Chacin, Hali Forstner