Abstract: A method includes storing basic input/output system (BIOS) firmware instructions at a first flash memory device included at an information handling system. The BIOS firmware includes an initial boot block. BIOS data is stored at a second flash memory device. A baseboard management controller validates instructions included at the initial boot block.

Abstract: A method includes storing basic input/output system (BIOS) firmware instructions at a first flash memory device included at an information handling system. The BIOS firmware includes an initial boot block. BIOS data is stored at a second flash memory device. A baseboard management controller validates instructions included at the initial boot block.

Abstract: An information handling system authenticates a key manifest of a memory with a hash of a key associated with the key manifest. When the key manifest is authentic, the system authenticates a boot policy manifest with the hash of first public key associated with the boot policy manifest. When the boot policy manifest is authentic, the system validates a pre-boot block of the memory based upon the hash of the pre-boot block stored in the boot policy manifest and directs a processor to execute the pre-boot code when the pre-boot block is valid. A processor executes the pre-boot code to execute a reset vector and to determine if the boot block is valid with hash of the boot block, and executes the boot code when the boot block is valid.

Abstract: An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

Abstract: An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

Abstract: A violation of a firmware access rule is detected, and an entry is generated at a log file stored at a baseboard management controller, the entry identifying the violation. In an embodiment, detecting the violation is in response to receiving a system management interrupt at an information handling system.

Abstract: A violation of a firmware access rule is detected, and an entry is generated at a log file stored at a baseboard management controller, the entry identifying the violation. In an embodiment, detecting the violation is in response to receiving a system management interrupt at an information handling system.

Abstract: A method and system are provided for updating an utilizing the contents of a non-essential region in a memory device in a computer system. A computer program is utilized to build an image file. The image file may include program code and data for operating a computer system. The image file includes an essential region for storing program code required to boot the computer system and a non-essential region for storing program code and data which is not required to boot the computer system. The non-essential program code may include graphics data, a language module, or diagnostic tools for the computer system. After building the image file, the image file is then copied to a memory device in the computer system. Finally, only the non-essential region in the memory device is updated. A method may also be utilized to execute program code contained in the non-essential region prior to executing program code contained in the essential region.

Abstract: A method and system are provided for updating an utilizing the contents of a non-essential region in a memory device in a computer system. A computer program is utilized to build an image file. The image file may include program code and data for operating a computer system. The image file includes an essential region for storing program code required to boot the computer system and a non-essential region for storing program code and data which is not required to boot the computer system. The non-essential program code may include graphics data, a language module, or diagnostic tools for the computer system. After building the image file, the image file is then copied to a memory device in the computer system. Finally, only the non-essential region in the memory device is updated. A method may also be utilized to execute program code contained in the non-essential region prior to executing program code contained in the essential region.

Abstract: A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, each disabled logical processor branches to the hard coded interrupt service routine. The interrupt service routine can be written to read only memory because the context, current instruction, and return state of the disabled logical processor are known, and the disabled logical processor will not need to write to system memory during the execution of the interrupt service routine. Following the handling of the interrupt by another logical processor of the computer system, each disabled logical processor returns to the halt state.

Abstract: A portable, articulated, hand-held exercising device comprising a pair of elongated tubular handles pivotally joined to each other by a common connector assembly. Each handle has an axis of rotation substantially normal to the other handle. Each handle has an independently adjustable torque/force characteristic. Thus, each handle may be rotated about its longitudinal axis with adjustable torque adjustment characteristics. The exerciser serves, in general, to condition the wrist, arms, chest, torso and shoulders of the user.