Abstract: A microcode update system includes at least one memory device having a code region and a data region, and a microcode update engine that receives a microcode update, and writes the microcode update to the data region of the at least one memory device. Subsequent to writing the microcode update to the data region of the at least one memory device, the microcode update engine utilizes initialization code in the code region of the at least one memory device to perform initialization operations. During a microcode update portion of the initialization operations, the microcode update engine identifies the microcode update in the data region of the at least one memory device, and performs microcode update operations using the microcode update in the data region of the at least one memory device.

Abstract: A microcode update system includes at least one memory device having a code region and a data region, and a microcode update engine that receives a microcode update, and writes the microcode update to the data region of the at least one memory device. Subsequent to writing the microcode update to the data region of the at least one memory device, the microcode update engine utilizes initialization code in the code region of the at least one memory device to perform initialization operations. During a microcode update portion of the initialization operations, the microcode update engine identifies the microcode update in the data region of the at least one memory device, and performs microcode update operations using the microcode update in the data region of the at least one memory device.

Abstract: A boot process security system includes a processing system including a plurality of registers, and at least one memory system that includes instructions that, when executed by the processing system, cause the processing system to provide a BIOS. During a Driver eXecution Environment (DXE) sub-process that is included in a boot process and that occurs prior to passing control of the boot process to any third-party drivers, the BIOS programs at least one of the plurality of registers in order to configure at least one secure subsystem. The BIOS then verifies, during the boot process, that the at least one secure subsystem has been configured to provide a predetermined configuration, and locks the at least one secure subsystem. The BIOS then confirms that the at least one secure subsystem has been locked prior to passing control of the boot process to any third-party drivers.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: A boot process security system includes a processing system including a plurality of registers, and at least one memory system that includes instructions that, when executed by the processing system, cause the processing system to provide a BIOS. During a Driver eXecution Environment (DXE) sub-process that is included in a boot process and that occurs prior to passing control of the boot process to any third-party drivers, the BIOS programs at least one of the plurality of registers in order to configure at least one secure subsystem. The BIOS then verifies, during the boot process, that the at least one secure subsystem has been configured to provide a predetermined configuration, and locks the at least one secure subsystem. The BIOS then confirms that the at least one secure subsystem has been locked prior to passing control of the boot process to any third-party drivers.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory.