Patents by Inventor Juan G. Revilla
Juan G. Revilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7568141Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.Type: GrantFiled: December 21, 2007Date of Patent: July 28, 2009Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
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Patent number: 7360059Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.Type: GrantFiled: February 3, 2006Date of Patent: April 15, 2008Assignee: Analog Devices, Inc.Inventors: Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Juan G. Revilla, Ravi P. Singh
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Patent number: 7313739Abstract: Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.Type: GrantFiled: December 31, 2002Date of Patent: December 25, 2007Assignee: Analog Devices, Inc.Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
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Patent number: 7272705Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.Type: GrantFiled: May 23, 2005Date of Patent: September 18, 2007Assignee: Analog Devices, Inc.Inventors: Juan G. Revilla, Ravi P. Singh, Charles P. Roth
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Patent number: 7174429Abstract: A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.Type: GrantFiled: December 28, 2001Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Juan G. Revilla, Ravi K. Kolagotla
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Patent number: 7124285Abstract: In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.Type: GrantFiled: March 29, 2001Date of Patent: October 17, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ryo Inoue, Juan G. Revilla
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Patent number: 7082516Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.Type: GrantFiled: September 28, 2000Date of Patent: July 25, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Juan G. Revilla, Ravi P. Singh
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Patent number: 7028129Abstract: A processor may include a processor core, which interprets and executes instructions, and a system bus interface, which enables the processor to communicate with a system. The system bus interface may include a fill bus and a DMA bus. The system bus interface may include a bridge between the fill bus and the DMA bus which enables the system bus interface to re-route information placed on the fill bus onto the DMA bus and back into the core.Type: GrantFiled: December 28, 2001Date of Patent: April 11, 2006Assignee: Intel CorporationInventors: Juan G. Revilla, Minh D. Tran
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Patent number: 6920515Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.Type: GrantFiled: March 29, 2001Date of Patent: July 19, 2005Assignees: Intel Corporation, Analog Devices, IncInventors: Juan G. Revilla, Ravi P. Singh, Charles P. Roth
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Patent number: 6874078Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.Type: GrantFiled: July 15, 2003Date of Patent: March 29, 2005Assignee: PTS CorporationInventors: Gerald G. Pechanek, Juan G. Revilla
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Patent number: 6789187Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.Type: GrantFiled: December 15, 2000Date of Patent: September 7, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Ravi Kolagotla, Juan G. Revilla
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Publication number: 20040148488Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.Type: ApplicationFiled: July 15, 2003Publication date: July 29, 2004Applicant: PTS CorporationInventors: Gerald G. Pechanek, Juan G. Revilla
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Publication number: 20040128596Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
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Patent number: 6606699Abstract: An apparatus for concurrently executing controller single instruction single data (SISD) instructions and single instruction multiple data (SIMD) processing element instructions comprising a combined controller and processing element. At least first and second simplex instructions each comprise a mode of operation bit, said mode of operation bit in the first simplex instruction specifying a controller SISD operation for execution by the controller, and the mode of operation bit in the second simplex instruction specifying a procesing element SIMD operation for execution by the processsing element. A very long instruction word (VLIW) contains said at least first and second simplex instructions.Type: GrantFiled: February 14, 2001Date of Patent: August 12, 2003Assignee: Bops, Inc.Inventors: Gerald G. Pechanek, Juan G. Revilla
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Publication number: 20030126367Abstract: A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Juan G. Revilla, Ravi Kolagotla
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Publication number: 20030126345Abstract: A processor may include a processor core, which interprets and executes instructions, and a system bus interface, which enables the processor to communicate with a system. The system bus interface may include a fill bus and a DMA bus. The system bus interface may include a bridge between the fill bus and the DMA bus which enables the system bus interface to re-route information placed on the fill bus onto the DMA bus and back into the core.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Juan G. Revilla, Minh D. Tran
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Publication number: 20020144100Abstract: In one embodiment, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may comprise a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. Restoring the future file may take more than one clock cycle.Type: ApplicationFiled: March 29, 2001Publication date: October 3, 2002Inventors: Ryo Inoue, Juan G. Revilla
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Publication number: 20020144041Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.Type: ApplicationFiled: March 29, 2001Publication date: October 3, 2002Inventors: Juan G. Revilla, Ravi P. Singh, Charles P. Roth
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Publication number: 20020078336Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Ravi Kolagotla, Juan G. Revilla
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Publication number: 20010032303Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.Type: ApplicationFiled: February 14, 2001Publication date: October 18, 2001Inventors: Gerald G. Pechanek, Juan G. Revilla