Patents by Inventor Juan M. Casas, JR.

Juan M. Casas, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069980
    Abstract: Method, computer program product, and computer system are provided. A first migration of a running logical partition (LPAR) is performed from a first-generation computer to a second-generation computer. Availability of a facility differs between the first- and second-generation computers. Upon completion of the first migration, an operating system of the running LPAR detects whether a required facility in use on the first-generation computer is available on the second-generation computer. Operating system takes an action to continue an orderly execution of the LPAR, the operating system, and threads of an application in the LPAR depending on the availability of the required facility. A second migration is performed of the running LPAR from the second-generation computer back to the first-generation computer. The required facility is available on the first-generation computer. The operating system restores access to threads of the application to the required facility.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Brian Frank Veale, Arnold Flores, Andre Laurent Albot, Juan M. Casas, JR.
  • Patent number: 11656933
    Abstract: A processor may receive a software fix package. The processor may apply an interim software code fix of the software fix package to software of a device, where the interim software code fix includes adjusting one or more tunable computing parameters to one or more first values. The processor may identify that a reboot of the device is recommended for application of a permanent code fix of the software fix package. The processor may identify that the device was not rebooted after receipt of the software fix package. The processor may determine that a dynamic reconfiguration event has taken place. The processor may apply, automatically, one or more second values for the one or more tunable computing parameters associated with the interim software code fix of the software fix package.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 23, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brian Frank Veale, Juan M. Casas, Jr., Arnold Flores, Michael Passaloukos
  • Publication number: 20230098905
    Abstract: A processor may receive a software fix package. The processor may apply an interim software code fix of the software fix package to software of a device, where the interim software code fix includes adjusting one or more tunable computing parameters to one or more first values. The processor may identify that a reboot of the device is recommended for application of a permanent code fix of the software fix package. The processor may identify that the device was not rebooted after receipt of the software fix package. The processor may determine that a dynamic reconfiguration event has taken place. The processor may apply, automatically, one or more second values for the one or more tunable computing parameters associated with the interim software code fix of the software fix package.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Brian Frank Veale, Juan M. Casas, JR., Arnold Flores, MICHAEL PASSALOUKOS
  • Patent number: 11520612
    Abstract: In an embodiment, a guest operating system (OS) running on a virtual machine (VM) detects a VM migration, where the embodiment comprises storing, by the guest OS, a VM identifier (VMID) provided by the VM and a first host identifier (HID) provided by a host computer system in a computer memory. The embodiment also comprises determining, by the guest OS, that the VM performs migrations that are transparent to the guest OS. The embodiment further comprises detecting, by the guest OS, that the VM has been migrated based on a comparison of the first HID to a second HID provided to the guest OS in response to an HID request from the guest OS.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Frank Veale, Juan M. Casas, Jr., Caleb Russell Olson, Amanda Liem
  • Patent number: 11436043
    Abstract: For a process of an operating system, it is detected that a live migration has occurred, the live migration comprising a change in a hardware characteristic of a computer system on which the process executes. A first message is broadcast to a set of processors, the first message causing each processor in the set of processors to enter a waiting state. While each of the set of processors is in the waiting state, a portion of a set of program instructions of the operating system is modified.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Frank Veale, Juan M. Casas, Jr., Caleb Russell Olson, Amanda Liem
  • Publication number: 20210141654
    Abstract: In an embodiment, a guest operating system (OS) running on a virtual machine (VM) detects a VM migration, where the embodiment comprises storing, by the guest OS, a VM identifier (VMID) provided by the VM and a first host identifier (HID) provided by a host computer system in a computer memory. The embodiment also comprises determining, by the guest OS, that the VM performs migrations that are transparent to the guest OS. The embodiment further comprises detecting, by the guest OS, that the VM has been migrated based on a comparison of the first HID to a second HID provided to the guest OS in response to an HID request from the guest OS.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Brian Frank Veale, Juan M. Casas, JR., Caleb Russell Olson, Amanda Liem
  • Publication number: 20210141664
    Abstract: For a process of an operating system, it is detected that a live migration has occurred, the live migration comprising a change in a hardware characteristic of a computer system on which the process executes. A first message is broadcast to a set of processors, the first message causing each processor in the set of processors to enter a waiting state. While each of the set of processors is in the waiting state, a portion of a set of program instructions of the operating system is modified.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Brian Frank Veale, Juan M. Casas, JR., Caleb Russell Olson, Amanda LIEM
  • Patent number: 10346327
    Abstract: A system and computer program product are provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 10346329
    Abstract: A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Publication number: 20180276156
    Abstract: A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Application
    Filed: October 24, 2017
    Publication date: September 27, 2018
    Applicant: International Business Machines Corporation
    Inventors: Juan M. Casas, JR., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Publication number: 20180276155
    Abstract: A system and computer program product are provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 27, 2018
    Applicant: International Business Machines Corporation
    Inventors: Juan M. Casas, JR., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Publication number: 20130179618
    Abstract: Provided are techniques for physically coupling, via a docking port, a first stand-alone computing device to a communication bus coupled to a set of processing resources; detecting, by the communication bus, the coupling; responsive to the detecting of the coupling, correlating the stand-alone computing device to a subset of the set of processing resources; signaling, by the communication bus, each resource of the subset of the coupling; and responsive to the signaling, dynamically configuring the stand-alone computing device and each resource of the subset to enable the stand-alone computing device to utilize each resource of the subset.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juan M. Casas, JR., Nikhil Hegde, Alexander Medvedev, Rashmi Narasimhan