Abstract: The systems and methods described can reduce high order temperature coefficients on the Hall plate sensitivity. A temperature coefficient circuit may include a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device and a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node. A plurality of resistors may be disposed in a signal path between output node of the first amplifier and an output node of the second amplifier. The plurality of resistors may be coupled to at least one voltage-to-current converter through one or more resistors taps. The voltage-to-current converter may generate at least one current signal that can be operable to apply a multiplication factor or a division divisor to an amplifier coupled to the voltage-to-current converter.

Abstract: A sensor integrated circuit can include sensors with differing levels of sensitivity, a first processing channel that responds to a first analog signal generated by a first sensor to generate a first processed signal, and a second processing channel that responds to a second analog signal generated by the second sensor to generate a second processed signal. Where the first sensor can include a pressure or optical sensing element, and the second sensor can include a pressure or optical sensing element. A checker circuit uses the processed signals to detect faults in the sensor integrated circuit.

Abstract: A sensor integrated circuit can include sensors with differing levels of sensitivity, a first processing channel that responds to a first analog signal generated by a first sensor to generate a first processed signal, and a second processing channel that responds to a second analog signal generated by the second sensor to generate a second processed signal. Where the first sensor can include a pressure or optical sensing element, and the second sensor can include a pressure or optical sensing element. A checker circuit uses the processed signals to detect faults in the sensor integrated circuit.

Abstract: A planar Hall effect element be formed upon or can include a P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hail effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.

Abstract: A sensor integrated circuit includes at least two processing channels responsive to the same or different analog input signals to generate respective processed signals. The two processing channels are non-homogenous and, in some embodiments have different processing accuracies. A checker circuit receives the first and second processed signals and is configured to detect a fault in the sensor integrated circuit when the first and second processed signals differ from each other by more than a predetermined amount.

Abstract: Hall effect elements are driven by current generators that use vertical epi resistors disposed away from an edge of a substrate upon which, within which, or over which, the Hall effect elements, the current generators, and the vertical epi resistors are disposed.

Abstract: A sensor integrated circuit includes at least two processing channels responsive to the same or different analog input signals to generate respective processed signals. The two processing channels are non-homogenous and, in some embodiments have different processing accuracies. A checker circuit receives the first and second processed signals and is configured to detect a fault in the sensor integrated circuit when the first and second processed signals differ from each other by more than a predetermined amount.

Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Abstract: A data storage circuit for storing data from volatile memory to non-volatile memory is powered by a low power charge pump circuit that is independent of the power for the volatile memory and that is activated upon power loss. The low power charge pump circuit includes an amplifier, a voltage-controlled oscillator, a charge pump core, and a voltage divider. The amplifier outputs a current according to a voltage difference between a reference input voltage and a feedback voltage output from the voltage divider. The current is converted to a voltage that controls the oscillator, which outputs a series of pulses to power the charge pump core. The charge pump core in turn provides the output voltage, which may be used to power an attached load. The attached load may be a programming port for an EEPROM.

Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Abstract: A sensor integrated circuit includes at least two processing channels responsive to the same or different analog input signals to generate respective processed signals. The two processing channels are non-homogenous and, in some embodiments have different processing accuracies. A checker circuit receives the first and second processed signals and is configured to detect a fault in the sensor integrated circuit when the first and second processed signals differ from each other by more than a predetermined amount.

Abstract: An integrated circuit with transmission line error detection comprises a substrate, a package enclosing the substrate, a lead extending from the inside of the package to the outside of the package, and a circuit supported by the substrate. The circuit includes an input circuit and an output circuit. A first wire is coupled between the output circuit and the lead and a second wire is coupled between the lead and the input circuit so that the input circuit receives a signal generated by the output circuit after the signal has been transmitted across the first and second wires.

Abstract: The present disclosure is directed to an electronic circuit having a Hall effect element and a resistor bridge, all disposed over a common semiconductor substrate. The resistor bridge includes a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, and a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series. The first set of resistive elements and the second set of resistive elements can be coupled in parallel. The resistor bridge can be configured to sense a stress value of the Hall effect element.

Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Abstract: A planar Hall effect element be formed upon or can include a the P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hall effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.

Abstract: The systems and methods described can reduce high order temperature coefficients on the Hall plate sensitivity. A temperature coefficient circuit may include a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device and a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node. A plurality of resistors may be disposed in a signal path between output node of the first amplifier and an output node of the second amplifier. The plurality of resistors may be coupled to at least one voltage-to-current converter through one or more resistors taps. The voltage-to-current converter may generate at least one current signal that can be operable to apply a multiplication factor or a division divisor to an amplifier coupled to the voltage-to-current converter.

Abstract: Hall effect elements are driven by current generators that use vertical epi resistors disposed away from an edge of a substrate upon which, within which, or over which, the Hall effect elements, the current generators, and the vertical epi resistors are disposed.

Abstract: The present disclosure is directed to an electronic circuit having a Hall effect element and a resistor bridge, all disposed over a common semiconductor substrate. The resistor bridge includes a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, and a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series. The first set of resistive elements and the second set of resistive elements can be coupled in parallel. The resistor bridge can be configured to sense a stress value of the Hall effect element.

Abstract: The systems and methods described can reduce high order temperature coefficients on the Hall plate sensitivity. A temperature coefficient circuit may include a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device and a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node. A plurality of resistors may be disposed in a signal path between output node of the first amplifier and an output node of the second amplifier. The plurality of resistors may be coupled to at least one voltage-to-current converter through one or more resistors taps. The voltage-to-current converter may generate at least one current signal that can be operable to apply a multiplication factor or a division divisor to an amplifier coupled to the voltage-to-current converter.

Abstract: A sensor integrated circuit includes at least two processing channels responsive to the same or different analog input signals to generate respective processed signals. The two processing channels are non-homogenous and, in some embodiments have different processing accuracies. A checker circuit receives the first and second processed signals and is configured to detect a fault in the sensor integrated circuit when the first and second processed signals differ from each other by more than a predetermined amount.