Patents by Inventor Juan ZENG
Juan ZENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250094674Abstract: Examples of methods are described herein. In some examples, a method includes generating, using a compensation machine learning model after training, a compensated model based on a three-dimensional (3D) object model. In some examples, the compensation machine learning model is trained by generating candidate compensation plans and evaluating, using a deformation machine learning model, the candidate compensation plans. In some examples, the method includes adjusting the 3D object model based on the compensated model to produce an adjusted model.Type: ApplicationFiled: July 30, 2021Publication date: March 20, 2025Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, LP.Inventors: Juheon LEE, Juan Carlos CATANA SALAZAR, Nathan MORONEY, Jun ZENG
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Patent number: 12229890Abstract: Examples of methods for model prediction are described herein. In some examples, a method includes predicting a compensated model. In some examples, the compensated model is predicted based on a three-dimensional (3D) object model. In some examples, a method includes predicting a deformed model. In some examples, the deformed mode is predicted based on the compensated model.Type: GrantFiled: January 31, 2020Date of Patent: February 18, 2025Assignee: Hewlett-Packard Development Company, L.P.Inventors: He Luan, Juan Carlos Catana Salazar, Jun Zeng
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Publication number: 20250051365Abstract: Provided herein are KRAS modulating compounds, such as compounds of Formula (I), (I-A), (I-B), (I-C), (I-C*), (I-D), (I-E), (I-F), (I-G), (I-H), (I-I), (I-J), or pharmaceutically acceptable salts, solvates, stereoisomers, atom labelled, or tautomers of any one thereof. The compounds provided herein are useful for modulating KRAS GD12 and/or other G12 mutants.Type: ApplicationFiled: September 20, 2024Publication date: February 13, 2025Inventors: Hong LIN, Juan LUENGO, Audrey HOSPITAL, Jin ZENG, Pei GAN
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Publication number: 20250053152Abstract: Examples of methods are described. In some examples, a method includes determining a quantification of a spatial neighborhood of a voxel of a build volume. In some examples, the method includes predicting, using a machine learning model, a manufacturing powder degradation based on the quantification and a position of the voxel.Type: ApplicationFiled: December 13, 2021Publication date: February 13, 2025Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Jacob Tyler WRIGHT, Sunil KOTHARI, Juan Carlos CATANA SALAZAR, Lei CHEN, Maria Fabiola LEYVA MENDIVIL, Jun ZENG
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Publication number: 20250021721Abstract: Examples of methods are described. In some examples, a method may include producing, by a processor, a density determination of a lattice structure. In some examples, the method may include producing, by the processor, a beam thickness determination of the lattice structure. In some examples, the method may include adjusting a beam thickness of the lattice structure based on the density determination and the beam thickness determination.Type: ApplicationFiled: November 23, 2021Publication date: January 16, 2025Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Wei HUANG, Juan Carlos CATANA SALAZAR, Jun ZENG
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Patent number: 12159840Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.Type: GrantFiled: June 23, 2020Date of Patent: December 3, 2024Assignee: Intel CorporationInventors: Zhiguo Qian, Gerald Pasdast, Juan Zeng, Peipei Wang, Ahmad Siddiqui, Lakshmipriya Seshan
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Publication number: 20220271912Abstract: Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Inventors: Gerald Pasdast, Peipei Wang, Lakshmipriya Seshan, Juan Zeng, Zuoguo Wu, Zhiguo Qian, Narasimha Lanka, Debendra Das Sharma, Swadesh Choudhary
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Publication number: 20210398906Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Zhiguo QIAN, Gerald PASDAST, Juan ZENG, Peipei WANG, Ahmad SIDDIQUI, Lakshmipriya SESHAN
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Publication number: 20180198185Abstract: A cavity resonator tuning diaphragm comprising a plurality of inner corrugations, the plurality of inner corrugations having a first depth. An outer corrugation located between the plurality of inner corrugations and a perimeter of the diaphragm is also included, the outer corrugation having a second depth greater than the first depth. The addition of the outer deep corrugation provides increased thermal stability and reduced required actuation voltage.Type: ApplicationFiled: March 12, 2018Publication date: July 12, 2018Applicant: Purdue Research FoundationInventors: Juan Zeng, Zhengan Yang, Dimitrios Peroulis
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Patent number: 9956744Abstract: A shell, a method of preparing the shell and an electronic product comprising the shell are provided. The shell may comprise: a metal shell body, a plastic part made of a resin, and an oxide layer formed between the metal body and the plastic part, joining the plastic part to the metal shell body, wherein the oxide layer contains corrosion pores having an average diameter of about 200 nm to about 2000 nm in the surface contacting the plastic part, and nanopores having a diameter of about 10 to 100 nm in the surface contacting the metal shell body, and a part of the resin is filled in the corrosion pore and corrosion pore.Type: GrantFiled: August 22, 2014Date of Patent: May 1, 2018Assignees: Shenzhen BYD Auto R&D Company Limited, BYD Company LimitedInventors: Jian Sun, Juan Zeng, Yunxia Zhang, Jun Cheng
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Patent number: 9917344Abstract: A cavity resonator tuning diaphragm comprising a plurality of inner corrugations, the plurality of inner corrugations having a first depth. An outer corrugation located between the plurality of inner corrugations and a perimeter of the diaphragm is also included, the outer corrugation having a second depth greater than the first depth. The addition of the outer deep corrugation provides increased thermal stability and reduced required actuation voltage.Type: GrantFiled: April 14, 2016Date of Patent: March 13, 2018Assignee: PURDUE RESEARCH FOUNDATIONInventors: Juan Zeng, Zhengan Yang, Dimitrios Peroulis
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Publication number: 20160336922Abstract: A cavity resonator tuning diaphragm comprising a plurality of inner corrugations, the plurality of inner corrugations having a first depth. An outer corrugation located between the plurality of inner corrugations and a perimeter of the diaphragm is also included, the outer corrugation having a second depth greater than the first depth. The addition of the outer deep corrugation provides increased thermal stability and reduced required actuation voltage.Type: ApplicationFiled: April 14, 2016Publication date: November 17, 2016Applicant: Purdue Research FoundationInventors: Juan Zeng, Zhengan Yang, Dimitrios Peroulis
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Publication number: 20140363623Abstract: A shell, a method of preparing the shell and an electronic product comprising the shell are provided. The shell may comprise: a metal shell body, a plastic part made of a resin, and an oxide layer formed between the metal body and the plastic part, joining the plastic part to the metal shell body, wherein the oxide layer contains corrosion pores having an average diameter of about 200 nm to about 2000 nm in the surface contacting the plastic part, and nanopores having a diameter of about 10 to 100 nm in the surface contacting the metal shell body, and a part of the resin is filled in the corrosion pore and corrosion pore.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Jian SUN, Juan ZENG, Yunxia ZHANG, Jun CHENG
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Publication number: 20140363658Abstract: An aluminum alloy, an aluminum alloy resin composite, a method of preparing aluminum alloy, and a method of preparing aluminum alloy-resin composite are provided. The aluminum alloy may comprise: an aluminum alloy substrate; and an oxide layer formed on the surface of the aluminum alloy substrate. The oxide layer comprises an outer surface and an inner surface. The outer surface contains corrosion pores having an average diameter of about 200 nm to about 2000 nm; and the inner surface contains nanopores having an average diameter of about 10 nm to about 100 nm.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Jian SUN, Juan ZENG, Jun CHENG