Patents by Inventor Juang-Ke Yeh
Juang-Ke Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6753569Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.Type: GrantFiled: December 31, 2001Date of Patent: June 22, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chang Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh
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Patent number: 6509603Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.Type: GrantFiled: March 27, 2001Date of Patent: January 21, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh
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Patent number: 6483159Abstract: A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.Type: GrantFiled: July 14, 2000Date of Patent: November 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh, Di-Son Kuo
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Publication number: 20020055205Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.Type: ApplicationFiled: December 31, 2001Publication date: May 9, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yai-Fen Lin, Chang Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh
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Patent number: 6358796Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.Type: GrantFiled: April 15, 1999Date of Patent: March 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chang-Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh
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Publication number: 20010029076Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.Type: ApplicationFiled: March 27, 2001Publication date: October 11, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh
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Patent number: 6246089Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.Type: GrantFiled: March 13, 2000Date of Patent: June 12, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh
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Patent number: 6121088Abstract: Form a split gate EEPROM memory device on a doped silicon semiconductor substrate starting with an initial oxide layer and form an undoped first polysilicon layer thereon. Then form a polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.Type: GrantFiled: September 17, 1998Date of Patent: September 19, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-ke Yeh, Di-Son Kuo
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Patent number: 6060360Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.Type: GrantFiled: April 14, 1997Date of Patent: May 9, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh
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Patent number: 6055183Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.Type: GrantFiled: October 24, 1997Date of Patent: April 25, 2000Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chou Ho, Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh
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Patent number: 6049484Abstract: A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.Type: GrantFiled: September 10, 1998Date of Patent: April 11, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chou Ho
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Patent number: 5903499Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.Type: GrantFiled: September 12, 1997Date of Patent: May 11, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Reay Peng, Jian-Hsing Lee, Juang-Ke Yeh, Ming-Chou Ho
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Patent number: 5828605Abstract: The present invention provides method to erase flash EEPROMS devices using a positive sine waveform (Vs) and negative Vg that drives a cell in to snapback breakdown to remove trapped electron in the tunnel oxide and improve device performance. The snapback breakdown operation of one cell in the array lowers the tunnel oxide electric field for all cells in the array. The snapback breakdown generates a substrate current that reduces the electric field thereby reducing electron and hole trapping.Type: GrantFiled: October 14, 1997Date of Patent: October 27, 1998Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Kuo-Reay Peng, Jian-Hsing Lee, Juang-Ke Yeh, Ming-Chon Ho
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Patent number: 5726933Abstract: The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.Type: GrantFiled: May 15, 1997Date of Patent: March 10, 1998Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hsing Lee, Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chou Ho