Abstract: A processing method for a first device connected with a plurality of external devices in a first communication mode and sharing a screen with the plurality of external devices, includes determining a second device from the plurality of external devices, in response to satisfying a first preset condition, continuing to share the screen with the plurality of external devices in a second communication mode, and sending screen data or data associated with a screen display content to the second device in the first communication mode, to cause the second device to replace the first device to continue to share the screen with another external device other than the second device in the plurality of external devices, and disconnecting a connection with the plurality of external devices in the second communication mode, in response to the second device successfully continuing to share the screen with the other external device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of memory cells located on a substrate. Each of the plurality of memory cells includes a transistor and a capacitor. The capacitor is electrically connected to the transistor. The capacitor includes a body portion, and at least one extension portion located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a capacitor structure. The base is provided with a capacitive contact structure. The capacitor structure is connected to the capacitive contact structure, and the capacitor structure includes a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure.

Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

Abstract: A semiconductor structure includes: a plurality of transistors located in a semiconductor layer; each of the transistors including a semiconductor body extending in a first direction and a gate structure covering at least one side surface of the semiconductor body; the first direction being a thickness direction of the semiconductor layer; a plurality of conductive pillars, each of the conductive pillars being located on a top surface of a corresponding semiconductor body and being in direct contact with the corresponding semiconductor body; a memory structure covering the plurality of conductive pillars.

Abstract: A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.

Abstract: The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

Abstract: A semiconductor structure and a method for manufacturing same are provided. The semiconductor structure includes: a doped conductive layer, doped with dopant ions; a metal conductive layer, located above the doped conductive layer; a nitrogen-containing dielectric layer, located above the metal conductive layer; a first molybdenum nitride layer, located between the doped conductive layer and the metal conductive layer and configured to be electrically connected to the doped conductive layer and the metal conductive layer; and a second molybdenum nitride layer, located between the metal conductive layer and the nitrogen-containing dielectric layer, where an atomic ratio of nitrogen atoms in the second molybdenum nitride layer is greater than an atomic ratio of nitrogen atoms in the first molybdenum nitride layer.

Abstract: A processing method for a first device connected with a plurality of external devices in a first communication mode and sharing a screen with the plurality of external devices, includes determining a second device from the plurality of external devices, in response to satisfying a first preset condition, continuing to share the screen with the plurality of external devices in a second communication mode, and sending screen data or data associated with a screen display content to the second device in the first communication mode, to cause the second device to replace the first device to continue to share the screen with another external device other than the second device in the plurality of external devices, and disconnecting a connection with the plurality of external devices in the second communication mode, in response to the second device successfully continuing to share the screen with the other external device.

Abstract: A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure comprises: providing a substrate comprising a first area for forming a P-channel Metal Oxide Semiconductor (PMOS) transistor and a second area for forming an N-channel Metal Oxide Semiconductor (NMOS) transistor; forming a channel layer on the surface of the first area of the substrate; adjusting the oxidation rate of the channel layer to reduce the difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the surfaces of the channel layer and the second area of the substrate to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

Abstract: Provided are a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method includes: providing a substrate; forming a plurality of bit line structures distributed at intervals on the substrate, each of the bit line structures including a conductive structure, a conductive barrier block and an insulative structure which are stacked sequentially, and the width of the conductive barrier block being less than the width of the conductive structure; and forming an air gap in contact with a side wall of each of the bit line structures.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure can improve performance of the semiconductor structure. The method for manufacturing the semiconductor structure includes: forming bit line structures on a substrate, each of the bit line structures including a conductive layer, a transition layer and a covering layer stacked sequentially, and a width of the transition layer being smaller than a width of the conductive layer; and forming air gaps on a top surface of the conductive layer and side surfaces of the transition layer. The air gaps not only can reduce influence of the covering layer on the conductive layer to prevent the resistance of the conductive layer from increasing, but also can reduce the parasitic capacitance between the bit line structures and the surrounding structures thereof, thereby improving the performance of the semiconductor structure.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.

Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.