Patents by Inventor Ju Bin SEO
Ju Bin SEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006362Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.Type: ApplicationFiled: January 18, 2023Publication date: January 4, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Bin Seo, Seok Ho Kim, Kwang Jin Moon, Ho-Jin Lee
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Publication number: 20230282528Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.Type: ApplicationFiled: August 29, 2022Publication date: September 7, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Bin SEO, Su Jeong PARK, Seok Ho KIM, Kwang Jin MOON
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Patent number: 11728297Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: GrantFiled: May 20, 2021Date of Patent: August 15, 2023Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Patent number: 11600552Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: June 10, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Publication number: 20230060360Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.Type: ApplicationFiled: April 7, 2022Publication date: March 2, 2023Inventors: Ju Bin SEO, Seok Ho KIM, Kwang Jin MOON
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Patent number: 11488860Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: GrantFiled: July 24, 2020Date of Patent: November 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-Il Choi, Atsushi Fujisaki
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Publication number: 20210296211Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: ApplicationFiled: June 10, 2021Publication date: September 23, 2021Inventors: Ju-Bin SEO, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Publication number: 20210272918Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Patent number: 11043445Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: April 17, 2019Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Patent number: 11018101Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: GrantFiled: April 30, 2019Date of Patent: May 25, 2021Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Publication number: 20200357690Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju Bin SEO, Ju-Il CHOI, Atsushi FUJISAKI
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Patent number: 10763163Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: GrantFiled: January 8, 2019Date of Patent: September 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-il Choi, Atsushi Fujisaki
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Publication number: 20200144158Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: ApplicationFiled: April 17, 2019Publication date: May 7, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin SEO, Su-Jeong PARK, Tae-Seong KIM, Kwang-Jin MOON, Dong-Chan LIM, Ju-Il CHOI
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Publication number: 20200075524Abstract: A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided.Type: ApplicationFiled: March 18, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Bin SEO, Dong Hoon LEE, Ju Il CHOI, Su Jeong PARK, Dong Chan LIM
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Publication number: 20200027784Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: ApplicationFiled: January 8, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju-bin SEO, Ju-ll CHOI, Atsushi FUJISAKI
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Publication number: 20190259718Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Patent number: 10325869Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component.Type: GrantFiled: January 12, 2018Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Publication number: 20190027450Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.Type: ApplicationFiled: January 12, 2018Publication date: January 24, 2019Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
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Patent number: 9461205Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer and a plurality of light emitting nanostructures. The base layer is formed of a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. Each of the light emitting nanostructures is disposed on the exposed regions of the base layer and includes nanocore formed of a first conductivity type semiconductor, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on side surfaces of the nanocore. Upper surfaces of the light emitting nanostructures are non-planar and contain portions free of the second conductivity-type semiconductor layer in order to prevent light emissions during device driving.Type: GrantFiled: July 22, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam Goo Cha, Hyun Seong Kum, Ju Bin Seo, Dong Hoon Lee
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Patent number: 9159882Abstract: A semiconductor light-emitting device includes a first conductive type semiconductor layer having a main surface, a plurality of vertical type light-emitting structures protruding upward from the first conductive type semiconductor layer; a transparent electrode layer covering the plurality of vertical type light-emitting structures; and an insulation-filling layer disposed on the transparent electrode layer. The insulation-filling layer extends parallel to the first conductive type semiconductor layer so as to cover the plurality of vertical type light-emitting structures. A selected one of the first conductive type semiconductor layer and the insulation-filling layer, which is disposed on a light transmission path through which light generated from the plurality of vertical type light-emitting structures is radiated externally, has an uneven outer surface.Type: GrantFiled: September 30, 2014Date of Patent: October 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Wook Hwang, Ju-Bin Seo, Ji-Hye Yeon, Geon-Wook Yoo, Dong-hoon Lee