Abstract: A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.

Abstract: A cathode active material with controlled rheological properties for lithium secondary batteries. In particular, the cathode active material for a lithium secondary battery includes: a core part comprising a lithium metal oxide; and a coating layer covering at least a portion of a surface of the core part and comprising an inorganic compound.

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VP represented by Equation (1) below is 4 mbar·Ah?1·sec?1 or less: Equation (1): VP=?P/(tmax×C).

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VT represented by Equation (1) below measured after manufacturing a test module by stacking four of the lithium secondary battery fully charged by being charged to 4.35 V is 4 Ah/sec or less: Equation (1): VT=Ctotal/t.

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VT represented by Equation (1) below measured after manufacturing a test module by stacking four of the lithium secondary battery fully charged by being charged to 4.35 V is 4 Ah/sec or less: Equation (1): VT=Ctotal/t.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: An efficient logging method and system is disclosed that can be used to recover from a failure in a transaction system. It is based on a differential logging scheme that allows commutative and associative recovery operations. The method includes the steps of taking a before-image of the primary database in main memory before an update to the primary database; taking an after-image of the primary database after the update; generating a differential log by applying bit-wise exclusive-OR (XOR) between the before-image and the after-image; and performing either a redo or undo operation by applying XOR between said one or more logs and the before-image. Since XOR operations are commutative and associative, correct recovery is possible regardless of the creation sequence of log records. The present invention improves the performance of a logging system by reducing the size of log records and by allowing parallel execution of recovery operations.

Abstract: An efficient logging method and system is disclosed that can be used to recover from a failure in a transaction system. It is based on a differential logging scheme that allows commutative and associative recovery operations. The method includes the steps of taking a before-image of the primary database in main memory before an update to the primary database; taking an after-image of the primary database after the update; generating a differential log by applying bit-wise exclusive-OR (XOR) between the before-image and the after-image; and performing either a redo or undo operation by applying XOR between said one or more logs and the before-image. Since XOR operations are commutative and associative, correct recovery is possible regardless of the creation sequence of log records. The present invention improves the performance of a logging system by reducing the size of log records and by allowing parallel execution of recovery operations.