Patents by Inventor Judge K. Arora
Judge K. Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230119260Abstract: Methods, non-transitory computer readable media, network traffic manager apparatuses, and systems that assist with mitigating DDoS attack using a hardware device includes determining when a received network packet in an established connection between a client and a destination server includes a connection identifier cookie. A connection validation cookie is generated based on at least data in the received network packet, when the determination indicates the received network packet includes the connection identifier cookie. The connection identifier cookie is compared against the generated connection validation cookie. The received network packet is dropped when the comparison indicates the connection validation cookie fails to match the connection identifier cookie.Type: ApplicationFiled: September 29, 2022Publication date: April 20, 2023Applicant: F5, Inc.Inventors: Sandeep AGARWAL, Pete THORNEWELL, Bruce ZURFLUH, Judge K. ARORA, Ravneet DHALIWAL
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Patent number: 6629238Abstract: The present invention provides a mechanism for predicting whether a predicate is written and a value of the predicate to be written. For one embodiment, a predicate predictor is used to predict whether a predicate, in some cases a stage predicate, is written and a value to be written for the predicate, using the branch type and branch prediction information supplied by a branch predictor. The predicted stage predicate value controls data hazard handling and data bypasses operations for intermediate stages of the processor's instruction execution pipeline. The predicted stage predicate value may be validated when the modulo-scheduled loop instruction is resolved at the back end of the instruction execution pipeline.Type: GrantFiled: December 29, 1999Date of Patent: September 30, 2003Assignee: Intel CorporationInventors: Judge K. Arora, Tse-Yu Yeh
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Patent number: 6598156Abstract: A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.Type: GrantFiled: December 23, 1999Date of Patent: July 22, 2003Assignee: Intel CorporationInventor: Judge K. Arora
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Patent number: 6442678Abstract: In one method, a processor comprises both a speculative register file to store speculative register values and an architectural register file to store architectural register values. An output of the architectural register file is coupled to an input of the speculative register file to update the speculative register file when a misspeculation is detected.Type: GrantFiled: December 31, 1998Date of Patent: August 27, 2002Assignee: Intel CorporationInventor: Judge K. Arora
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Patent number: 6401195Abstract: In one method, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.Type: GrantFiled: December 30, 1998Date of Patent: June 4, 2002Assignee: Intel CorporationInventors: Judge K. Arora, Harshvardhan P. Sharangpani, Ghassan W. Khadder
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Patent number: 6393556Abstract: An apparatus and method for changing privilege level in a processor configured to pipeline instructions are presented. The processor includes a first memory storing an architectural privilege level that is set at a first privilege level, a second memory storing a plurality of instructions, and a pipeline including a plurality of processing stages. A first instruction is fetched from the memory and a determination is made whether the first instruction requires the first privilege level be changed to a second privilege level, and in response thereto, any subsequent instructions are flushed from the pipeline before recording the second privilege level in the first memory.Type: GrantFiled: October 30, 1998Date of Patent: May 21, 2002Assignee: Intel CorporationInventor: Judge K. Arora
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Publication number: 20020042874Abstract: An apparatus and method for changing privilege level in a processor configured to pipeline instructions are presented. The processor includes a first memory storing an architectural privilege level that is set at a first privilege level, a second memory storing a plurality of instructions, and a pipeline including a plurality of processing stages. A first instruction is fetched from the memory and a determination is made whether the first instruction requires the first privilege level be changed to a second privilege level, and in response thereto, any subsequent instructions are flushed from the pipeline before recording the second privilege level in the first memory.Type: ApplicationFiled: October 30, 1998Publication date: April 11, 2002Inventor: JUDGE K. ARORA
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Patent number: 6304960Abstract: A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the determined target addresses is selected, using predicted branch directions. The selected target address is compared with a predicted target address, and resolved branch directions are compared with predicted branch directions. A misprediction is indicated if either comparison fails.Type: GrantFiled: August 6, 1998Date of Patent: October 16, 2001Assignee: Intel CorporationInventors: Tse-Yu Yeh, Michael Paul Corwin, Judge K. Arora, Sujat Jamil, Sailesh Kottapalli
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Patent number: 6304955Abstract: Performing hazard detection in a processor that exhibits register latencies between execution units. The opcode classes of producer and consumer instructions are determined. Using these opcode classes, the register latency between the producer and consumer instructions is determined, and a register status signal is sent.Type: GrantFiled: December 30, 1998Date of Patent: October 16, 2001Assignee: Intel CorporationInventor: Judge K. Arora
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Patent number: 6272520Abstract: A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.Type: GrantFiled: December 31, 1997Date of Patent: August 7, 2001Assignees: Intel Corporation, Hewlette PackardInventors: Harshvardhan Sharangpani, Rajiv Gupta, Judge K. Arora
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Patent number: 6219781Abstract: Performing hazard detection in the presence of predication. The status of a consumer register associated with a consumer instruction is determined. The status and value of a predicate associated with the consumer instruction is also determined. A hazard signal is then sent based the status of the consumer register, the status of the predicate, and the value of the predicate.Type: GrantFiled: December 30, 1998Date of Patent: April 17, 2001Assignee: Intel CorporationInventor: Judge K. Arora
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Patent number: 6199144Abstract: A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.Type: GrantFiled: December 31, 1997Date of Patent: March 6, 2001Assignee: Intel CorporationInventors: Judge K. Arora, William R. Bryg, Stephen G. Burger, Gary N. Hammond, Michael L. Ziegler
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Patent number: 6119218Abstract: A method and apparatus for prefetching data in a computer system that inces a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.Type: GrantFiled: July 8, 1999Date of Patent: September 12, 2000Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Judge K. Arora, Jack D. Mills, Jerome C. Huck
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Patent number: 6115808Abstract: Performing hazard detection using status and mask vectors. Predicate status and mask vectors are generated. From the predicate status vector it is determined if a predicate is pending, and from the predicate mask vector it is determined if the predicate is needed.Type: GrantFiled: December 30, 1998Date of Patent: September 5, 2000Assignee: Intel CorporationInventor: Judge K. Arora
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Patent number: 6065115Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.Type: GrantFiled: April 10, 1998Date of Patent: May 16, 2000Assignee: Intel CorporationInventors: Harshvardhan P. Sharangpani, Gary N. Hammond, Hans J. Mulder, Judge K. Arora
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Patent number: 5948095Abstract: A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.Type: GrantFiled: December 31, 1997Date of Patent: September 7, 1999Assignee: Intel CorporationInventors: Judge K. Arora, Jack D. Mills, Jerome C. Huck
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Patent number: 5860017Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.Type: GrantFiled: June 28, 1996Date of Patent: January 12, 1999Assignee: Intel CorporationInventors: Harshvardhan P. Sharangpani, Gary N. Hammond, Hans J. Mulder, Judge K. Arora
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Patent number: 5832260Abstract: A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict.Type: GrantFiled: December 29, 1995Date of Patent: November 3, 1998Assignee: Intel CorporationInventors: Judge K. Arora, Gary N. Hammond, Harshvardhan P. Sharangpani