Abstract: A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

Abstract: Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

Abstract: A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

Abstract: A system for effecting and monitoring a real-time process that is participated in by multiple participants over a network. In one embodiment, multiple components of the system include: at least one participant computer with a display; at least one server coupled to the at least one participant computer through the network; and at least one memory device that stores instructions. When the instructions are executed, they cause a processor to periodically collect real-time data regarding the real-time process, and periodically update a display with a graphical representation of a current state of the process using the real-time data. The instructions also cause the processor to receive participant inputs via the display, wherein the participant inputs include changes to the real-time data. The processor also updates the display to reflect the changes to the real-time data in response to the participant inputs.

Abstract: A method for effecting and monitoring a real-time, multi-participant process via a network. In one embodiment, the method includes periodically collecting real-time data regarding the real-time process, and periodically updating a display comprising a graphical representation of a current state of the process using the real-time data. The method further includes receiving user inputs via the display, wherein the user inputs include changes to the real-time data, and in response to the user inputs, updating the display to reflect the changes to the real-time data.