Abstract: A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit.

Abstract: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

Abstract: A method and computer device for determining the cache memory configuration. The method includes allocating an amount of cache memory from a first memory level of the cache memory, and determining a read transfer time for the allocated amount of cache memory. The allocated amount of cache memory then is increased and the read transfer time for the increased allocated amount of cache memory is determined. The allocated amount of cache memory continues to be increased and the read transfer time determined for the each allocated amount until all of the cache memory in all of the cache memory levels has been allocated. The cache memory configuration is determined based on the read transfer times from the allocated portions of the cache memory. The determined cache memory configuration includes the number of cache memory levels and the respective capacities of each cache memory level.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.

Abstract: A system and method for testing memory management functions of a data processing system. A controller is configured to start and monitor progress of one or more programs, and each of the one or more programs is configured to start a number of threads as specified by input parameter values. At least one or more of the threads are configured to create, modify, and delete one or more memory areas. A feedback activity measures performance characteristics of the data processing system while the one or more threads are executing and selectively adjusts the parameter values in response to the performance characteristics relative to target performance characteristics.

Abstract: A method and apparatus for testing data coherency in a file system implemented on a data processing arrangement. A record of file addresses is maintained for addresses that are not targeted by write operations, and word address ranges for write operations are selected from the record of file addresses not targeted by other write operations. A plurality of asynchronous write operations that specify word address ranges and data to be written are issued. For each completed write operation, an asynchronous read operation that references the address range of the completed write operation is issued. The data returned from the read operation is verified against data issued in the completed write operation. The record of file addresses not targeted by write operations is updated when the verifying step is complete.

Abstract: A method and apparatus for testing a computing arrangement. In various embodiments, a plurality of parameter definitions are established, including a static-value parameter and a dynamic-value parameter. A plurality of sets of parameter values are established in association with the parameter definitions. A results storage area has portions respectively associated with the sets of parameter values. A test program is associated with the parameter definitions and is configured to execute using one set of parameter values at a time. The test program inputs a parameter value associated with a static parameter, automatically generates a value for each dynamic parameter, and exercises the computing arrangement using the parameter values in a set, the value of each parameter affecting behavior of the computing arrangement via the test program.

Abstract: A method and apparatus for controlling a distribution of sizes of input/output (I/O) operations in testing a data processing system. A plurality of I/O operations of different sizes are issued in response to a set of distribution parameter values. Each distribution parameter value specifies a number of I/O operations to issue for one or more sizes of I/O operations. The I/O operations are verified for correctness after completion. While issuing the I/O operations, performance characteristics of the data processing system are measured. In response to the performance characteristics relative to target performance characteristics, the distribution parameter values are selectively adjusted.

Abstract: A method and apparatus for creating sets of parameters values for scenarios for testing a computing arrangement. In a first phase of parameter optimization, each parameter value is adjusted one at a time, and a measured performance characteristic controls when to stop considering alternative values for the parameter. When the performance characteristic satisfies selected criteria relative to the target data set, another parameter value is selected for adjustment. Each parameter is assigned to a group as a function of the level of change of the performance characteristic from one value of the parameter to another. In a second phase of parameter optimization, each parameter value is adjusted in order of parameters in groups that exhibit greater levels of change of the performance characteristic to parameters in groups that exhibit lesser levels of change of the performance characteristic.