Patents by Inventor Judith LaRocca
Judith LaRocca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7751371Abstract: A variable rate transmission system where a packet of variable rate data is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channel.Type: GrantFiled: July 24, 2006Date of Patent: July 6, 2010Assignee: QUALCOMM IncorporatedInventors: Ephraim Zehavi, David S. Miller, Judith LaRocca
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Patent number: 7649939Abstract: An apparatus to determine the inverse transform of a block of encoded data the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: GrantFiled: September 20, 2004Date of Patent: January 19, 2010Assignee: QUALCOMM IncorporatedInventors: Judith LaRocca, A. Chris Irvine, Jeffrey A. Levin
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Patent number: 7593582Abstract: Apparatus, systems and methods for using the selection of an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: May 22, 2007Date of Patent: September 22, 2009Assignee: QUALCOMM IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 7388993Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: October 17, 2005Date of Patent: June 17, 2008Assignee: QUALCOMM IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Publication number: 20070248274Abstract: Apparatus, systems and methods for using the selection of an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: ApplicationFiled: May 22, 2007Publication date: October 25, 2007Applicant: QUALCOMM INCORPORATEDInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 7167460Abstract: A variable rate transmission system where a packet of variable rate data is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channel.Type: GrantFiled: May 8, 2001Date of Patent: January 23, 2007Assignee: Qualcomm IncorporatedInventors: Ephraim Zehavi, David S. Miller, Judith LaRocca
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Publication number: 20060262756Abstract: A variable rate transmission system where a packet of variable rate data is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channel.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Inventors: Ephraim Zehavi, David Miller, Judith LaRocca
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Publication number: 20060034532Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: ApplicationFiled: October 17, 2005Publication date: February 16, 2006Inventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 6996595Abstract: In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.Type: GrantFiled: June 13, 2001Date of Patent: February 7, 2006Assignee: Qualcomm IncorporatedInventors: Judith LaRocca, Ann Chris Irvine
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Patent number: 6975773Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: July 29, 2003Date of Patent: December 13, 2005Assignee: Qualcomm, IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 6876704Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: GrantFiled: June 6, 2001Date of Patent: April 5, 2005Assignee: Qualcomm, IncorporatedInventors: Judith LaRocca, A. Chris Irvine, Jeffrey A. Levin
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Patent number: 6870885Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: GrantFiled: June 6, 2001Date of Patent: March 22, 2005Assignee: Qualcomm IncorporatedInventors: Judith LaRocca, A. Chris Irvine, Jeffrey A. Levin
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Publication number: 20050038843Abstract: An apparatus to determine the inverse transform of a block of encoded data the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: ApplicationFiled: September 20, 2004Publication date: February 17, 2005Inventors: Judith LaRocca, A. Irvine, Jeffrey Levin
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Publication number: 20030020965Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: ApplicationFiled: June 6, 2001Publication date: January 30, 2003Inventors: Judith LaRocca, A. Chris Irvine, Jeffrey A. Levin
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Publication number: 20020181027Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.Type: ApplicationFiled: June 6, 2001Publication date: December 5, 2002Inventors: Judith LaRocca, A. Chris Irvine, Jeffrey A. Levin
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Publication number: 20020176118Abstract: In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.Type: ApplicationFiled: June 13, 2001Publication date: November 28, 2002Inventors: Judith LaRocca, Ann Chris Irvine
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Publication number: 20010024432Abstract: A variable rate transmission system where a packet of variable rate data is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channel.Type: ApplicationFiled: May 8, 2001Publication date: September 27, 2001Applicant: Qualcomm, IncorporatedInventors: Ephraim Zehavi, David S. Miller, Judith LaRocca
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Patent number: 6292476Abstract: A variable rate receiving system where a packet of variable rate data is reassembled on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is received on a traffic channel and at least one overflow channel. Also described is a transmission system for transmitting the data on the traffic channel and at least one additional overflow channel.Type: GrantFiled: September 24, 1997Date of Patent: September 18, 2001Assignee: Qualcomm Inc.Inventors: Ephraim Zehavi, David S. Miller, Judith LaRocca
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Patent number: 5777990Abstract: A variable rate transmission system where a packet of variable is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channels.Type: GrantFiled: April 16, 1997Date of Patent: July 7, 1998Assignee: Qualcomm IncorporatedInventors: Ephraim Zehavi, David S. Miller, Judith LaRocca