Patents by Inventor Judith Maget

Judith Maget has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7592875
    Abstract: An ILO circuit has a plurality of oscillator stages which are coupled to one another by means of a “tank lock” coupling. The coupling leads to an improved synchronization of the individual oscillator stages and thus to a reduced phase noise. Any desired LC oscillator topology can be used, not just the topology with PMOS and NMOS transistors. It is also possible to use SOI transistors, that is to say transistors formed on an SOI substrate. The bulk terminals of the transistors may be coupled not only to a supply voltage but, for example, also to a center potential, a reference voltage source, to ground, in floating fashion and/or to the source terminal.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: September 22, 2009
    Assignee: Infineon Technologies AG
    Inventors: Judith Maget, Marc Tiebout
  • Publication number: 20080030282
    Abstract: An ILO circuit has a plurality of oscillator stages which are coupled to one another by means of a “tank lock” coupling. The coupling leads to an improved synchronization of the individual oscillator stages and thus to a reduced phase noise. Any desired LC oscillator topology can be used, not just the topology with PMOS and NMOS transistors. It is also possible to use SOI transistors, that is to say transistors formed on an SOI substrate. The bulk terminals of the transistors may be coupled not only to a supply voltage but, for example, also to a center potential, a reference voltage source, to ground, in floating fashion and/or to the source terminal.
    Type: Application
    Filed: September 10, 2004
    Publication date: February 7, 2008
    Inventors: Judith Maget, Marc Tiebout
  • Patent number: 7019384
    Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: March 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Judith Maget, Marc Tiebout
  • Patent number: 6906904
    Abstract: An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is made of highly doped well terminal regions having a deep depth, for example formed as collector deep implantation regions. This reduces the series resistance of the tunable capacitance. The integrated, tunable capacitance can be used for example in integrated voltage-controlled oscillator circuits in which a high quality factor is demanded.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: June 14, 2005
    Assignee: Infineon Technologies AG
    Inventor: Judith Maget
  • Publication number: 20050067674
    Abstract: An integrated, tuneable capacitance is disclosed that is based on an MOS transistor. In order to improve the linearity characteristics of the tuning characteristic of the varactor, the invention provides for part of the gate region to be doped with the conductance type p, and part to be doped with the conductance type n. Provision is also made for the gate and source/drain regions not to overlap one another, but to be separated from one another on a horizontal plane. This results in a wider variation ratio with a lower series resistance.
    Type: Application
    Filed: August 13, 2004
    Publication date: March 31, 2005
    Inventor: Judith Maget
  • Patent number: 6864528
    Abstract: An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal regions in the conventional CMOS varactors. For this purpose, by way of example, well-type regions or collector deep implantation regions may be provided, with which the depleted regions occurring in the event of large tuning voltages extend significantly further into the semiconductor body. The varactor with a large tuning range can be produced without additional outlay in mass production methods and can be used, for example, in phase-locked loops.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: March 8, 2005
    Assignee: Infineon Technologies AG
    Inventor: Judith Maget
  • Publication number: 20040114302
    Abstract: An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal regions in the conventional CMOS varactors. For this purpose, by way of example, well-type regions or collector deep implantation regions may be provided, with which the depleted regions occurring in the event of large tuning voltages extend significantly further into the semiconductor body. The varactor with a large tuning range can be produced without additional outlay in mass production methods and can be used, for example, in phase-locked loops.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 17, 2004
    Inventor: Judith Maget
  • Publication number: 20040094824
    Abstract: An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is made of highly doped well terminal regions having a deep depth, for example formed as collector deep implantation regions. This reduces the series resistance of the tunable capacitance. The integrated, tunable capacitance can be used for example in integrated voltage-controlled oscillator circuits in which a high quality factor is demanded.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 20, 2004
    Inventor: Judith Maget
  • Publication number: 20040065939
    Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Inventors: Judith Maget, Marc Tiebout