Abstract: A circuit arrangement and method interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect capable of routing separate serial command, data and clock signals between functional blocks in the device. The concurrent serial interconnect utilizes a plurality of serial ports that are selectively coupled to one another by an interface controller to define one or more logical communication channels between two or more of the serial ports. Each serial port is coupled via a point-to-point interconnection with a port interface in a functional block. In addition, the concurrent serial interconnect facilitates the design of an integrated circuit device by supporting the addition of a serial interconnect to an assemblage of functional blocks, with each functional block associated with one of a plurality of serial ports in the serial interconnect.

Abstract: The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended to provide. In accordance with exemplary embodiments, optimal efficiency in using the shared memory is achieved by buffering memory accesses which will not increase overhead during a memory write cycle. As a result, interruptions by one controller while another controller is accessing the shared memory are reduced to a minimum.