Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.

Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.

Abstract: A system for enhancing fault tolerances and security of a computing system having a system clock through monitoring the computing system for at least one of a series of security attacks and upon detection of security attacks, switching the system from the system clock to a secure clock.

Abstract: An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i.e., never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area.

Abstract: A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.

Abstract: A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

Abstract: A low-cost computer system which includes a single shared memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the "appetite" for main system memory (unlike that of a display memory) is difficult to satisfy, the memory granularity problem can be addressed by programmably reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements.