Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract: Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.

Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

Abstract: System and method is disclosed for breaking an integrated circuit design to be printed into two or more exposures by lithographic equipment, each of the two or more exposures has at least the minimum pitch. Together, these multiple exposures print an integrated circuit design that could not be printed in one exposure alone.

Abstract: System and method is disclosed for breaking a design to be printed into two or more exposures, each of which has at least the minimum pitch. Together, these multiple exposures print a design that could not be printed in one exposure alone.

Abstract: An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.