Patents by Inventor Judy L. Sutor

Judy L. Sutor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage
    Patent number: 5631187
    Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: May 20, 1997
    Assignee: Motorola, Inc.
    Inventors: John P. Phipps, Stephen P. Robb, Judy L. Sutor, Lewis E. Terry
  • Semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage
    Patent number: 5365099
    Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: November 15, 1994
    Assignee: Motorola, Inc.
    Inventors: John P. Phipps, Stephen P. Robb, Judy L. Sutor, Lewis E. Terry
  • CMOS high gain amplifier utilizing positive feedback
    Patent number: 4701718
    Abstract: A CMOS operational amplifier comprises an input stage for receiving first and second potentials, a bias stage and first and second gain stages. In order to improve the frequency response, capacitors are employed to provide positive feedback. The biasing stage maintains the output in its active region, and avoids the necessity of external biasing.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: October 20, 1987
    Assignee: Motorola Inc.
    Inventors: Robert S. Wrathall, Judy L. Sutor