Abstract: A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fibre-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.

Abstract: A fiber-channel loop interface circuit that includes a dedicated transmit-frame buffer for loop initialization and responses (“responses” are non-data frames sent in response to commands or inquiries from other nodes). Having a dedicated transmit-frame buffer allows one port of a dual-port node to be transmitting initialization or response frames while another port is transmitting data frames, response frames, or initialization frames. Either or both ports can also be simultaneously receiving frames. The system includes a channel node having dual ports, each supporting a fiber-channel arbitrated-loop serial communications channel, and dedicated frame buffers within the channel node for loop initialization and responses. In some embodiments, the dedicated frame buffers are configured as on-chip buffers and include: two inbound non-data buffers coupled to the two ports, a data-frame buffer coupled to both ports, and an outbound transmit-frame buffer coupled to at least one of the ports.

Abstract: Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory.

Abstract: Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node.

Abstract: Dedicated receive buffers for receiving non-data frames are provided for each port of a two-port node in a fibre-channel arbitrated-loop serial communications channel design. The improved communications channel system and method includes a channel node having dual ports each supporting a communications channel, both ports interfaced from a single interface chip, and a dedicated on-chip frame buffer located on the chip for receiving frames. The dedicated on-chip frame buffer includes two inbound non-data buffers, one coupled to each of two ports, wherein inbound non-data frames from each port are received into the respective inbound non-data buffer. The system further includes an off-chip buffer, wherein received non-data frames are received into one of the non-data-frame buffers and transferred from the non-data-frame buffer to the off-chip buffer. A data-frame buffer is operatively coupled to both ports to receive data frames from the ports, and move the data frames to the off-chip buffer.

Abstract: A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fiber-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.

Abstract: A module for connection to a computer network has a plurality of ports for exchanging data with the network. First and second buffers store data received through separate ones of the ports, the first buffer also stores data to be transmitted through all of the ports. An error (CRC) checker is responsive to a CRC code associated with data received by one of the ports to verify the integrity of the associated data. A CRC generator generates a CRC code for data to be transmitted through one of the ports. A gate is connected between the CRC generator and the buffers to transfer to-be-transmitted data stored in the first buffer to the CRC generator and to transfer received data stored in the second buffer to the CRC generator. A comparator is connected to the CRC generator and to the second buffer and is responsive to the CRC code generated by the CRC generator and the CRC code stored in the second buffer to verify the integrity of received data stored in the second buffer.

Abstract: A 16-bit data block is partitioned into upper 5-bit and 3-bit sub-blocks and lower 5-bit and 3-bit sub-blocks. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively, to selectively complement the output sub-block to adjust running disparity.

Abstract: Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node.

Abstract: Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory.