Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to the cache, (ii) detect a collision among the access requests, (iii) queue at least two first requests of the access requests that establish a speculative collision, the speculative collision occurring where the first requests access a given congruence class in the cache and (iv) delay a line allocation to the cache caused by a cache miss of a given one of the first requests while the given congruence class has at least N outstanding line fills in progress.

Abstract: An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to the cache, (ii) detect a collision among the access requests, (iii) queue at least two first requests of the access requests that establish a speculative collision, the speculative collision occurring where the first requests access a given congruence class in the cache and (iv) delay a line allocation to the cache caused by a cache miss of a given one of the first requests while the given congruence class has at least N outstanding line fills in progress.

Abstract: A reusable software block is adapted to control multiple instantiations of a peripheral device within a system. A device hardware abstraction layer defines offset values for registers of the peripheral device and a data structure for the peripheral device. A platform hardware abstraction layer defines an address map of the system, and is adapted to initialize each instantiation of the peripheral device via calls to the device hardware abstraction layer.

Abstract: File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to each of the plurality of design files in a first environment. An index is generated correlating each design file and its respective file path. In use, a file path in a second environment of an application is defined for each design file, and the index is applied to the file paths in the second environment to define full file paths for each design file through the first and second environments. The design files are then applied to the application using the full file paths.

Abstract: A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.

Abstract: A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in response to a first signal indicating a delay in a transfer between a first master of a plurality of masters and a slave on the bus, and (C) controlling the bus mastership using the first arbitration scheme in response to a second signal ending the delay in the transfer between the first master and the slave.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: A method and apparatus for receiving packets from a bus. A packet is received at an interface to the bus. The packet is parsed, and a determination is made whether to retain the packet from the parsing of the packet. The packet is placed in a buffer with a header. The packet is moved from the buffer to another bus using information located within the header, wherein repeated parsing of the packet to move the packet to another bus is unnecessary.

Abstract: A method and apparatus in a data processing system for multiple bus arbitration, wherein the data processing system includes a first bus connected to a second bus by a bridge. In response to receiving a request for a target device from a master device connected to a first bus, a determination is made as to whether the target device is connected to the first bus. The bridge is selected in response to determining that the target device is located on the second bus. The bridge initiates a request for the second bus in response to the selection of the bridge. The first bus and the second bus are connected to each other by the bridge in response to the bridge receiving a grant to the second bus, wherein the master device transfers data between the master device and the target device across the bridge.

Abstract: An electronic circuit coordinates accesses to a register shared among multiple system resources by managing the priority of each system resource relative to others. When a priority register access is initiated, a signal is generated to block a simultaneous or overlapping register access by another system resource. If another register access is already in operation, it will be completed before the priority register access operates on the shared register. Otherwise, if the priority register access operates on the register first, the non-priority register access is held off until the priority register access completes. A method coordinates the potentially simultaneous or overlapping register accesses by multiple system resources to a shared register. When a priority register access initiates, a lookahead signal issues to set a busy flag that blocks competing register accesses until the priority register access completes.

Abstract: An improved data processing system and in particular an improved data processing system that more effectively manages a shared resource within a data processing system. More specifically, a method and apparatus for managing access to a shared resource between a plurality of devices simultaneously requesting access to the shared resource. The present invention implements a design that combines a priority configuration and a shifting sequential configuration. The access is controlled by an arbiter that determines access to the shared resource by granting first, to priority devices and then to the highest priority shifting sequential device requesting access within one clock cycle of a device terminating its request for access to the shared resource.