Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.

Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract: A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

Abstract: A semiconductor device with improved short channel characteristics is formed with a buried amorphous region comprising a retrograde impurity region having the impurity concentration peak of the semiconductor substrate. The buried amorphous region, formed below the channel region, suppresses diffusion of displaced atoms and holes from the source/drain regions and reduces the resistance against latch-up phenomenon, thereby improving short channel characteristics.

Abstract: A semiconductor device is formed having a low voltage transistor in a logic core portion and a high voltage transistor in an input/output portion. The low voltage transistor is formed by ion implanting nitrogen into the surface and forming a gate oxide layer on the nitrogen implanted surface portion of the semiconductor substrate in the logic core region. The implanted nitrogen retards the growth of the gate oxide layer in the nitrogen implanted area, thereby enabling formation of gate oxide layers having different thicknesses.

Abstract: A semiconductor device comprising a miniaturized transistor with high-speed performance is formed with an ultra thin gate oxide layer. The ultra thin gate oxide layer is formed retarding its growth on a nitrogen-rich silicon substrate. Embodiments include ion implanting impurity to displace nitrogen atoms from a nitride layer on the substrate and to force the displaced nitrogen atoms into the surface portion of the semiconductor substrate. The nitrogen atoms retard the growth of the gate oxide layer, thereby enabling formation of an ultra thin gate oxide.

Abstract: A semiconductor device is formed having a gate electrode and a gate oxide comprising a central portion and edge portions having a thickness greater than that of the edge portions. Nitrogen is ion implanted into the surface of the semiconductor substrate to retard the growth of the central portion of the gate oxide, thereby enabling formation of gate oxide having a thin central portion and thicker edge portions.

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.