Patents by Inventor Jue HONG

Jue HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250245366
    Abstract: The present disclosure relates to a method and apparatus for generating a data tuple for secure computation, a medium, and a device. The method is applied to a first participant, and the method includes: separately obtaining a first pseudo-random number pair and a second pseudo-random number pair by jointly executing the R-OT protocol with a second participant twice; and generating a first element slice of a data tuple for secure computation based on the two pseudo-random number pairs, where the data tuple includes the first element slice and a second element slice, and the second element slice is generated by the second participant.
    Type: Application
    Filed: November 22, 2024
    Publication date: July 31, 2025
    Inventors: Qizhi ZHANG, Daode ZHANG, Quanwei CAI, Jue HONG, Ye WU
  • Publication number: 20250209845
    Abstract: A model federated fine-tuning method, a text classification method and apparatus, a medium, and a device. The method includes: performing word segmentation on a text sample, and generating an embedding vector corresponding to each of a plurality of segmented words by using a second model; determining, from the plurality of segmented words, a target segmented word having classification utility for a text category marked by a classification label; performing noise perturbation processing on embedding vectors corresponding to other segmented words in the plurality of segmented words except the target segmented word to obtain a perturbation vector; and collaboratively fine-tuning a model parameter of a first model with a server and another client based on the perturbation vector, an embedding vector corresponding to the target segmented word, and the classification label.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 26, 2025
    Inventors: Xicong SHEN, Yang LIU, Huiqi LIU, Jue HONG, Bing DUAN, Ye WU, Di WU
  • Publication number: 20230206133
    Abstract: Disclosed are a model parameter adjusting method and device, a storage medium and a program product. The method includes: performing classification processing on input data by using a classification model obtained through training based on secure multi-party computing, to obtain classification prediction values of the classification model (S201); performing reduction processing on the classification prediction values (S202); performing normalization processing on the classification prediction values subjected to the reduction processing, to obtain a normalization result of the classification prediction values (S203); and updating a parameter of the classification model according to the normalization result of the classification prediction values (S204).
    Type: Application
    Filed: March 9, 2023
    Publication date: June 29, 2023
    Applicant: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Qingyou YANG, Kai HE, Jinghua JIANG, Jue HONG
  • Patent number: 8168538
    Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 1, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Tian-Jue Hong
  • Publication number: 20100301304
    Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Applicant: Macronix International Co., Ltd.
    Inventors: SHIH-HUNG CHEN, TIAN-JUE HONG
  • Patent number: 6828208
    Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: December 7, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-De Lin, Hsiao-Kang Wang, Tian-Jue Hong, Shih-Liang Chou, Wen-Cheng Lien
  • Publication number: 20040147135
    Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 29, 2004
    Inventors: Tsung-De Lin, Hsiao-Kang Wang, Tian-Jue Hong, Shih-Liang Chou, Wen-Cheng Lien
  • Publication number: 20040146643
    Abstract: A method of determining the deposition temperature, especially inside the reaction chamber of a chemical vapor deposition station. The method includes placing a deposition substrate inside the reaction chamber, forming a layer of metal silicide over the deposition substrate, measuring the silicon/metal atomic ratio and finding the deposition temperature according to a pre-determined temperature versus silicon/metal atomic ratio relationship. The method permits immediate determination as well as real-time monitoring of deposition temperature inside the station.
    Type: Application
    Filed: January 24, 2003
    Publication date: July 29, 2004
    Inventors: Shih-Liang Chou, Tsung-Chin Wu, Tsung-De Lin, Tian-Jue Hong, Kou-Yow Tseng, Wen-Cheng Lien
  • Publication number: 20030168430
    Abstract: An etching method with less waste gases. Firstly, provide a substrate covered by a dielectric layer, and put both the substrate and the dielectric layer into a chamber that is coupled with a power source and a C3F8 reactive gases source. Next, provide a plasma inside the chamber under an environment with a low RF power, and a low pressure. Finally, terminate the existence of the plasma and move both the substrate and the etched dielectric later out the chamber.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Applicant: Macronix International Co., Ltd.
    Inventors: Kuo-Wei Shyu, Shou-Yi Tseng, Tian-Jue Hong, Jung-Yi Wu, Yen-Wen Chen