Patents by Inventor Jue-Hwang Sim

Jue-Hwang Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected
    Patent number: 7419909
    Abstract: Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Kim, Jae-Kwan Park, Dong-Hwa Kwak, Su-Jin Ahn, Yoon-Moon Park, Jue-Hwang Sim, Jang-Ho Park, Sang-Yong Park
  • Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected
    Publication number: 20080085581
    Abstract: Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an
    Type: Application
    Filed: December 29, 2006
    Publication date: April 10, 2008
    Inventors: Jin-Ho Kim, Jae-Kwan Park, Dong-Hwa Kwak, Su-Jin Ahn, Yoon-Moon Park, Jue-Hwang Sim, Jang-Ho Park, Sang-Yong Park