Patents by Inventor Jue-Jye Chen

Jue-Jye Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5900644
    Abstract: The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: May 4, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Lan Ying, Yuan-Chang Huang, Jue-Jye Chen, Yuh-Jier Mii
  • Patent number: 5702956
    Abstract: The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: December 30, 1997
    Assignee: Taiwan Semiconductor Manufactoring, Company Ltd
    Inventors: Shu-Lan Ying, Yuan-Chang Huang, Jue-Jye Chen, Yuh-Jier Mii
  • Patent number: 5514610
    Abstract: A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed through a polysilicon gate structure, into the underlying channel region. The ability to reproducibly place the desired dopant at the desired channel location, is dependent on the implant conditions as well as the reproducibility of the thicknesses of the layers the implant has to penetrate. This process has been designed to remove some of the variables and thus result in optimized device characteristics.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: May 7, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yeh-Jye Wann, Jue-Jye Chen