Patents by Inventor JUE OUYANG

JUE OUYANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142930
    Abstract: A semiconductor apparatus and a method of manufacturing the same are provided. A semiconductor apparatus includes a first nitride semiconductor layer, a second nitride semiconductor layer, an electrode, a dielectric structure, a field plate, a plurality of height compensators, and a plurality of vias. The second nitride semiconductor layer is on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The electrode contacts the second nitride semiconductor layer. The dielectric structure is disposed on the second nitride semiconductor layer and covers the electrode. The field plate is in the dielectric structure. The height compensators are in the dielectric structure and are disposed on the electrode and the field plate, respectively. The vias extend into the dielectric structure and contact top surfaces of the height compensators, respectively.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
    Inventors: Xiao ZHANG, Jue OUYANG, Han PENG, Jianjun ZHOU
  • Publication number: 20240222423
    Abstract: A semiconductor device having improved leakage current characteristics includes a semiconductor substrate with first and second nitride-based semiconductor layers so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. A doped III-V nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer. The doped layer has a substantially inverted trapezoidal cross-sectional shape with a longer inverted trapezoid base as an upper surface of the doped III-V nitride-based semiconductor layer and a width of the cross-sectional shape decreasing as the distance away from the upper surface increases. A gate electrode is disposed on or above the doped III-V semiconductor layer and positioned on or above the longer inverted trapezoid base. At least two source/drain (S/D) electrodes are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 4, 2024
    Inventors: Xiao ZHANG, Lijie ZHANG, Jue OUYANG, Wen-Yuan HSIEH
  • Patent number: 11862721
    Abstract: A semiconductor device includes a semiconductor substrate, first and second nitride-based semiconductor layers, S/D electrodes, a gate electrode, and a first passivation layer. The first nitride-based semiconductor layer is disposed over the semiconductor substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a 2DEG region. The S/D electrodes is disposed over the second nitride-based semiconductor layer. The gate electrode is disposed between the S/D electrodes. The first passivation layer is disposed over the second nitride-based semiconductor layer. Edges of the first and second nitride-based semiconductor layers and the first passivation layer collectively form a stepped sidewall over the semiconductor substrate.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 2, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Yulong Zhang, Jue Ouyang, Wei Huang, Jheng-Sheng You
  • Patent number: 11854887
    Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: December 26, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Weixing Du, Yulong Zhang, Jue Ouyang, Minghong Chang
  • Publication number: 20220302296
    Abstract: A semiconductor device includes a semiconductor substrate, first and second nitride-based semiconductor layers, S/D electrodes, a gate electrode, and a first passivation layer. The first nitride-based semiconductor layer is disposed over the semiconductor substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a 2DEG region. The S/D electrodes is disposed over the second nitride-based semiconductor layer. The gate electrode is disposed between the S/D electrodes. The first passivation layer is disposed over the second nitride-based semiconductor layer. Edges of the first and second nitride-based semiconductor layers and the first passivation layer collectively form a stepped sidewall over the semiconductor substrate.
    Type: Application
    Filed: September 30, 2020
    Publication date: September 22, 2022
    Inventors: Yulong ZHANG, Jue OUYANG, Wei HUANG, Jheng-Sheng YOU
  • Publication number: 20220122885
    Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.
    Type: Application
    Filed: April 10, 2020
    Publication date: April 21, 2022
    Inventors: WEIXING DU, YULONG ZHANG, JUE OUYANG, MINGHONG CHANG