Abstract: A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM circuit) at any time during normal operation of the device. Internal circuits are provided to decode the respective commands and send them to the different independent memory banks of the integrated circuit memory device. A local precharge control unit (or circuit) is present inside each of the memory banks that can receive and process the decoded precharge commands. If certain specified timing conditions are met, the local precharge control unit can issue and store a precharge request for a specific bank. The precharge request can be held back until all timing requirements are fulfilled. The precharge request can then be automatically executed.

Abstract: A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM circuit) at any time during normal operation of the device. Internal circuits are provided to decode the respective commands and send them to the different independent memory banks of the integrated circuit memory device. A local precharge control unit (or circuit) is present inside each of the memory banks that can receive and process the decoded precharge commands. If certain specified timing conditions are met, the local precharge control unit can issue and store a precharge request for a specific bank. The precharge request can be held back until all timing requirements are fulfilled. The precharge request can then be automatically executed.

Abstract: A digital delay phase locked loop, to quickly perform the phase lock on an input clock signal. The digital delay phase locked circuit has a delay apparatus, a buffer, a phase comparator, an adder-register, a clock divider and a demultiplexer. After a delay operation performed on the input clock signal by the delay apparatus, the phase locked clock signal is output via the buffer. The above two signals are then compared with each other using the phase comparator to output a comparison signal to the adder-register for addition/subtraction delay. Being controlled by the clock divider, the objective of fast phase lock is achieved by the addition/subtraction operation of the demultiplexer.

Abstract: A selective memory refresh circuit for refreshing a memory cell array. The memory cell array has a plurality of word lines connected to a plurality of word line selection circuits for determining if a particular word line needs to be refresh during a refresh cycle. Each word line refresh selection circuit further has a word line address latching device for receiving a word line pre-decode signal, a release signal, a triggering signal and outputting a word line latching signal and a word line refresh compare circuit for receiving the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the word line latching signal is at a high level, memory cells attached to the word line are refreshed. On the contrary, when the word line latching signal is at a low level, memory refresh for that word line is skipped.

Abstract: A memory refresh circuit is connected to a plurality of block memories via a plurality of word line drivers respectively connected to the block memories. The memory refresh circuit comprises a plurality of row address latches, a plurality of row address strobe monitors, and a row address counter. Each of the row address latches is respectively paired by electrical connection with one of the row address strobe monitors, and each pair of row address latches and row address strobe monitors is respectively connected to one of the block memories. The row address counter is connected to the row address latches to which it transmits a plurality of different row addresses. When a memory refresh signal is delivered to one of the row address strobe monitors, the corresponding row address latch latches the address to be refreshed to perform the refresh operation.

Abstract: A sense amplifier can be used with a high-speed IC memory device, which sense amplifier can help reduce the sensing latency during read operations to the memory device so as to allow fast access speed to the memory device. The sense amplifier includes a first-stage circuit, coupled to the bit lines of the memory device, for amplifying the differential data signal on the bit lines. Furthermore, a second-stage circuit has an input side coupled to receive the output signal from the first-stage circuit and an output side coupled to the bit lines, and is used for amplifying the output signal from the first-stage circuit and feeding the amplified signal back to the bit lines. The first-stage circuit and the second-stage circuit in combination constitute a positive feedback amplification loop coupled to the bit lines for amplifying the differential data signal on the bit lines to a detectable level.

Abstract: A voltage regulator capable of improving system response. The voltage regulator includes a feedback circuit and an operational amplifier. The input terminal of the feedback circuit is coupled to an output voltage terminal for attenuating signals coming out of the output terminal. The operational amplifier comprises a pre-amplifier, a clamping circuit and a power amplifier, all serially connected together. The input terminals of the pre-amplifier are respectively coupled to the output terminal of the feedback circuit and an input voltage terminal. The pre-amplifier is a device for amplifying differential voltage between input voltage signals and feedback voltage signals. The clamping circuit is a device for clamping amplified differential voltage from the pre-amplifier between a pre-defined voltage range. The power amplifier is a device for increasing the power of the differential voltage signals.

Abstract: A sense amplifier circuit for a semiconductor memory device. The sense amplifier of this invention has four more NMOS transistors than a conventional amplifier. The gate terminals of two of the NMOS transistors are connected to a write enable line. The gate terminals of the other two NMOS transistors are connected to a first and a second node point, which are in turn connected to a bit line and a complementary bit line, respectively. Through a feedback circuit provided by these four additional NMOS transistors, two of the NMOS transistors are switched on during a write cycle to provide a ground connection so that voltage level of the sense amplifier is rapidly pulled down. Since the latching speed of the sense amplifier is increased, the operating speed of the memory is increased, as well. In addition, partial writing of data can be avoided.

Abstract: A method for making hollow pendants of copper plate without any holes therein so that electrolyte does not flow into the hollow of the pendants during electroplating. These hollow pendants can hold their beautiful surface a long time without being corroded by electrolyte solvent flowing into and slowly seeping out of the hollow parts of a pendant. Copper plate is cut and press-formed into half-pieces, two half-pieces are clamped together and welded tightly with silver, the hollow product undergoes grinding and polishing and is finally electroplated to complete the finished product with no holes. Consequently, its brilliant surface can not be spoiled by electrolyte solvent seeping out of any tiny holes.