Patents by Inventor Jueinai Raynien Kwo

Jueinai Raynien Kwo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6495407
    Abstract: A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial defects that are detectable by high resolution transmission electron microscopy are formed. If the MOS structure is a MOS-FET then metal contacts are provided in conventional fashion. A post-metallization anneal can result in FETs that are substantially free of drain current/voltage hysteresis. MOS-FETs made according to the novel method can be produced with high yield and can have significantly increased lifetime, as compared to some prior art GaAs-based MOS-FETs.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: December 17, 2002
    Assignee: Agere Systems Inc.
    Inventors: Minghwei Hong, Jenn-Ming Kuo, Jueinai Raynien Kwo, Joseph Petrus Mannaerts, Yu-Chi Wang
  • Patent number: 6480633
    Abstract: An electro-optic device comprising an electro-optic crystal substrate, an optical waveguide path in the crystal adjacent the substrate surface and an electrode spaced from the surface by a buffer layer is provided with enhanced operating stability by forming the buffer layer of a transparent electronically conductive material. Preferred buffer materials are electronically conductive gallium-indium-oxide and electronically conductive zinc-indium-tin-oxide.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: November 12, 2002
    Assignee: Agere Systems Inc.
    Inventors: Robert McLemore Fleming, Rafael Nathan Kleiman, Jueinai Raynien Kwo, John William Osenbach, Gordon Albert Thomas
  • Patent number: 6469357
    Abstract: We have found that a single crystal, single domain oxide layer of thickness less than 5 nm can be grown on a (100) oriented GaAs-based semiconductor substrate. Similar epitaxial oxide can be grown on GaN and GaN-based semiconductors. The oxide typically is a rare earth oxide of the Mn2 0 3 structure (e.g., Gd2O3). The oxide/semiconductor interface can be of high quality, with low interface state density, and the oxide layer can have low leakage current and high breakdown voltage. The low thickness and high dielectric constant of the oxide layer result in a MOS structure of high capacitance per unit area. Such a structure advantageously forms a GaAs-based MOS-FET.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: October 22, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Minghwei Hong, Ahmet Refik Kortan, Jueinai Raynien Kwo, Joseph Petrus Mannaerts
  • Patent number: 6404027
    Abstract: A high dielectric rare earth oxide of the form Mn2O3 (such as, for example, Gd2O3 or Y2O3) is grown on a clean silicon (100) substrate surface under an oxygen partial pressure less than or equal to 10−7 torr to form an acceptable gate oxide (in terms of dielectric constant (∈˜18) and thickness) that eliminates the tunneling current present in ultra-thin conventional SiO2 dielectrics and avoids the formation of a native oxide layer at the interface between the silicon substrate and the dielectric. Epitaxial films can be grown on vicinal silicon substrates and amorphous films on regular silicon substrates to form the high dielectric gate oxide.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Minghwei Hong, Ahmet Refik Kortan, Jueinai Raynien Kwo, Joseph Petrus Mannaerts
  • Patent number: 6271069
    Abstract: Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga2O3, and with low midgap interface state density (e.g., at most 1×1011 cm−2 eV−1 at 20° C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300° C. in air, or above about 700° C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: August 7, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Young-Kai Chen, Alfred Yi Cho, William Scott Hobson, Minghwei Hong, Jenn-Ming Kuo, Jueinai Raynien Kwo, Donald Winslow Murphy, Fan Ren
  • Patent number: 5962883
    Abstract: Disclosed are articles that comprise an oxide layer on a GaAs-based semiconductor body, with metal layers on the oxide and the body facilitating application of an electric field across the oxide layer. The interface between the oxide and the semiconductor body is of device quality. Contrary to teachings of the prior art, the oxide is not essentially pure Ga.sub.2 O.sub.3, but instead has composition Ga.sub.x A.sub.y O.sub.z, where A is an electropositive stabilizer element adapted for stabilizing Ga in the 3+ oxidation state. Furthermore, x.gtoreq.0, z is selected to satisfy the requirement that both Ga and A is substantially fully oxidized and y/(x+y) is greater than 0.1. Stabilizer element A typically is selected from Sc, Y, the rare earth elements and the alkaline earth elements. Articles according to the invention exemplarily comprise a planar enchancement mode MOS-FET with inversion channel. A method of making articles as described above is also disclosed.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: October 5, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Minghwei Hong, Jueinai Raynien Kwo, Donald Winslow Murphy
  • Patent number: 5948216
    Abstract: The present applicants have discovered a method for making thin films comprising tantalum oxide that enhances the dielectric constant with or without TiO.sub.2 doping. Specifically, applicants have discovered sputtering Ta.sub.2 O.sub.5 in an oxygen-rich ambient at a temperature in excess of 450.degree. C. and preferably in excess of 550.degree. C., produces a new crystalline phase thin film having enhanced dielectric properties.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: September 7, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Robert J. Cava, Shang Y. Hou, Jueinai Raynien Kwo, Eric W. Seelig, Roderick K. Watts
  • Patent number: 5821171
    Abstract: A high quality interface between a GaAs-based semiconductor and a Ga.sub.2 O.sub.3 dielectric an be formed if the semiconductor surface is caused to have less than 1% of a monolayer impurity coverage at completion of the first monolayer of the Ga.sub.2 O.sub.3 on the surface. This is achieved, for instance, by preparing the surface of a GaAs wafer under UHV conditions in a first growth chamber, transferring the wafer through a transfer module under UHV to a second growth chamber that is also under UHV, and growing the dielectric by evaporation of Ga.sub.2 O.sub.3 from a solid source, the process carried out such that the integrated impurity exposure of the surface is at most 100 Langmuirs. Articles according to the invention have low interface state density (<10.sup.11 /cm.sup.2 .multidot.eV) and interface recombination velocity (<10.sup.4 cm/s). Semiconductor/Ga.sub.2 O.sub.3 structures according to the invention can be used advantageously in a variety of electronic or optoelectronic devices, e.g.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: October 13, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Minghwei Hong, Jueinai Raynien Kwo, Joseph Petrus Mannaerts, Matthias Passlack, Fan Ren, George John Zydzik