Patents by Inventor Juergen Bareither

Juergen Bareither has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock-independent latch setup-and-hold time in a combined D-type latch and flip-flop
    Patent number: 6097230
    Abstract: A combined D-type latch and D-type flip-flop circuit where the latch setup-and-hold time is independent of the clock state. This is accomplished in one method by rerouting the data path to the Master to provide equivalent delays to both the Master and the Slave. In a second method, a clocking circuit provides on-board clocking where the data ia always latched first into the Slave, and after a fixed delay, the data are latched into the Master.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: August 1, 2000
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Juergen Bareither
  • Protective circuit for BiCMOS/CMOS circuitry in hybrid VCC systems during H operation
    Patent number: 5831806
    Abstract: The present invention relates to a protective circuit for BiCMOS/CMOS circuitry in hybrid VCC systems during H operation. The object of the invention is to create such a protective circuit, which has the least possible influence on the circuitry employing it and only takes up a small amount of space. In order to attain such aim a protective circuit monitors the voltage (VOH) present at its output (AUS) by comparison with a predetermined voltage (REF) and when such predetermined voltage is exceeded it terminates H operation. The protective circuit is so designed that it only taps a negligible monitoring current component (Iex') from the output (AUS).
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: November 3, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Juergen Bareither