Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.

Abstract: A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respect

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure.

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer.

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respective

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs.

Abstract: A method for forming an interconnection structure for a semiconductor device is provided.

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure.

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer.

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap.

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se