Abstract: The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

Abstract: The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

Abstract: Technologies are provided for measuring a programming current (PC) for a memory cell (MC) of a one-time programmable read-only memory array. The MC includes a fuse equivalent circuit (FEC) that includes a first current path (CP) having a first node, a second CP having a fuse of the memory cell and a second node, and a third CP. The PC is split into a first current, a second current and a third current that flow over the first CP, the second CP, and the third CP, respectively. A first voltage applied along the first path is divided to generate a second voltage at the first node, and an output voltage generated by an operational amplifier controls the second current to maintain a third voltage at the second node at substantially the same value as the second voltage so that the second current has a sufficiently low value and does not burn the fuse.

Abstract: Technologies are provided for measuring a programming current (PC) for a memory cell (MC) of a one-time programmable read-only memory array. The MC includes a fuse equivalent circuit (FEC) that includes a first current path (CP) having a first node, a second CP having a fuse of the memory cell and a second node, and a third CP. The PC is split into a first current, a second current and a third current that flow over the first CP, the second CP, and the third CP, respectively. A first voltage applied along the first path is divided to generate a second voltage at the first node, and an output voltage generated by an operational amplifier controls the second current to maintain a third voltage at the second node at substantially the same value as the second voltage so that the second current has a sufficiently low value and does not burn the fuse.

Abstract: Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a first transistor, a second transistor, and a fuse with a first end and a second end. The second transistor is selectively operable to couple the first end of the fuse to a ground. The first bitline is coupled to the first transistor of each of the bitcells of one column. The second bitline is coupled to the second end of the fuse of each of the bitcells of the column. The first transistor of each of the bitcells of the column is selectively operable to couple the first end of the fuse to the first bitline.

Abstract: A comparator includes a differential amplifier having first and second input terminals and first and second output terminals. An input stage is operable to receive first and second input signals. The input stage includes first and second capacitors coupled to the first and second input terminals, respectively. Circuitry is operable to selectively couple the first input signal to the first capacitor and the second input signal to the second capacitor, while coupling the first and second capacitors to the first and second output terminals, respectively, during an offset cancellation phase, and selectively couple the second input signal to the first capacitor and the first input signal to the second capacitor, while isolating the first and second capacitors from first and second output terminals during a comparison phase.

Abstract: A digitally controlled filter tuning method and corresponding WLAN (Wireless Local Area Network) communication devices and integrated circuit chips are provided. A WLAN communication signal is filtered by a tunable filter. A cut-off frequency of the tunable filter is tuned by a feedback loop. Tuning the cut-off frequency includes comparing by a comparator an output signal emitted by the tunable filter to a reference signal and emitting by the comparator a comparator signal indicative of the difference between the output signal and the reference signal. Further, tuning the cut off frequency comprises receiving the comparator signal by a tuning controller and setting by the tuning controller the cut-off frequency of the tunable filter based on the comparator signal by applying a digital tuning word to the tunable filter. The described filter tuning technique may reduce product and manufacturing costs while providing enhanced tuning accuracy.

Abstract: A digitally controlled filter tuning method and corresponding WLAN (Wireless Local Area Network) communication devices and integrated circuit chips are provided. A WLAN communication signal is filtered by a tunable filter. A cut-off frequency of the tunable filter is tuned by a feedback loop. Tuning the cut-off frequency includes comparing by a comparator an output signal emitted by the tunable filter to a reference signal and emitting by the comparator a comparator signal indicative of the difference between the output signal and the reference signal. Further, tuning the cut-off frequency comprises receiving the comparator signal by a tuning controller and setting by the tuning controller the cut-off frequency of the tunable filter based on the comparator signal by applying a digital tuning word to the tunable filter. The described filter tuning technique may reduce product and manufacturing costs while providing enhanced tuning accuracy.