Abstract: A semiconductor component is described which includes two zones of opposite conductivity type having a pn junction therebetween, and in which one zone is formed of a monocrystalline semiconductor substrate body and the other zone is produced in the semiconductor body by a doping process, such, for example, as by an implantation or diffusing process. Before the diffusion or implantation takes place, a zone is created at or near the substrate surface which has a disturbed crystal lattice. The diffusion or implantation then takes place through the disturbed zone. A process for producing such a semiconductor component is also described.The other zone may also be produced after the disturbed crystal lattice is produced in the portion of the substrate body which portion will later become the second zone.

Abstract: This invention relates to an inverse planar transistor in which a base region of one conductivity type is formed in a semiconductor body of the opposite conductivity type adjacent a planar surface thereof. The collector of the transistor is provided by a Schottky contact on a portion of the outer face of the base region. A highly doped protective ring of the opposite conductivity type to that of the base region is provided for the Schottky contact. An enlarged thickness of the passivation layer adjacent the opening therethrough to provide an effective guard ring. A relatively highly doped buried layer of said opposite conductivity type is located in the semiconductor body below and spaced from the inner surface of the base region. The portion of the semiconductor body lying between the base region and the buried layer together with the buried layer form the emitter of the transistor. A highly doped region of the said opposite conductivity type extends from the planar surface to the buried layer.

Abstract: A process for suppressing parasitic components, in particular parasitic diodes and transistors, in integrated circuits which have, in particular, inversely operated transistors, in which a semiconductor substrate of the first conductivity type as introduced therein a highly doped zone of a second conductivity type which is opposite to the first conductivity type and which extends to a surface of the semiconductor substrate. A semiconductor layer of the second conductivity type is epitaxially deposited on the surface and the semiconductor layer further has produced therein zones of differing conductivity type which form at least one component which is electrically insulated from adjacent components.

Abstract: A process for producing an inversely operated transistor in a body of semiconductor material which has arranged on its surface collector, base and emitter zones and wherein the base is doped by ion implantation so that minority charge carriers injected from the emitter zone into the base zone are accelerated in the direction towards the collector zone due to an inner drift field in the base zone.

Abstract: A ring or lattice-shaped groove or trench is etched into a surface of a Si monocrystal layer. At least one boundary of the so-etched groove or trench is coated with a strip-shaped layer of an oxidation-blocking material, such as Si.sub.3 N.sub.4 and the area of the substrate adjacent to the Si.sub.3 N.sub.4 layer and/or the substrate area enclosed by such layer is provided with a relatively thick SiO.sub.2 layer which extends deeper into the Si surface than does the SiN.sub.4 layer, while the Si surface within the groove or trench remains uncoated. The so-obtained arrangement is then thermally oxidized under conditions sufficient to at least partially fill the groove or trench with SiO.sub.2. Thereafter, the oxidation-blocking layer and at least a part of the SiO.sub.2 layer which is outside the ring or lattice-shaped trench is removed by a suitable etchant from the monocrystalline surface and the thus uncovered Si surface is further processed to produce small pn-junctions.

Abstract: The surface of a semiconductor substrate, such as a silicon crystal, is uniformly coated with a layer of Si.sub.3 N.sub.4 and at least two selectively spaced windows are provided therein. The uncovered silicon surface within such windows is then coated with a layer of SiO.sub.2. Next, a SiO.sub.2 area within a first window along with a portion of the adjacent Si.sub.3 N.sub.4 areas are coated with a photo-lacquer mask while the substrate surface area beneath the second window is doped with a select dopant. This procedure is then reversed and the Photo-lacquer mask is removed from the first window and applied onto the second window while the substrate surface area beneath the first window is contacted with select dopant to produce a doped zone. In this manner, considerable tolerance for positioning of a diffusion mask is provided.