Abstract: A video telecommunication connection is established via a landline telecommunications network and an IP multimedia subsystem telecommunications network using a media gateway control function of at least one Internet multimedia-media gateway device in the IP multimedia subsystem telecommunications network. An H.223 multiplex level usable for a telecommunication connection is exposed to an H.223 protocol negotiation, in carrying out an H.245 protocol negotiations for setting up the H.223 protocol negotiations connection for a telecommunication connection. A media gateway control function device is informed when the H.223 logic channels are open by H.245 signaling, thereby enabling the Internet multimedia-media gateway device of the IP multimedia subsystem telecommunications network to carry out at least part of the setup.

Abstract: In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A method and a circuit system for actuating a number of modules. The method is carried out using the circuit system, which implements a flexible trigger mechanism.

Abstract: A circuit arrangement for signal pick-up and signal generation and a method for operating this circuit arrangement. The circuit has at least one timer module for providing a time basis to a plurality of time control modules connected to it, and has a time routing unit, which is connected to it for the interconnection of the named modules and their signals.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.

Abstract: A method and a circuit system for actuating a number of modules. The method is carried out using the circuit system, which implements a flexible trigger mechanism.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A companion chip for engine control signal processing. The companion chip includes a signal pre-processing circuit which is developed for the computation of an interpolation and a tangential slope of an engine control signal.

Abstract: A signal acquisition device which receives an input signal, a physical data and a timing data to generate an output data. The signal acquisition device keeps monitoring the input signal for a valid edge. When a valid edge is detected, the signal acquisition device reads the physical data from a physical data processing module and a timing data from a timing module to generate the output data which comprises the new state of the input signal, the physical data and the timing data. The output data is written to a storage arrangement and also sent out to CPU or any other devices.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A circuit arrangement for signal pick-up and signal generation and a method for operating this circuit arrangement. The circuit has at least one timer module for providing a time basis to a plurality of time control modules connected to it, and has a time routing unit, which is connected to it for the interconnection of the named modules and their signals.

Abstract: A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.

Abstract: The invention relates to a communication method and interface between a companion chip (CC) and a microcontroller (MC), a communication protocol being transmitted, having a first group of data (10) being drawn on for direct, non-real-time-critical access to the chip (CC), and a second group of data (20) based on which a real-time-critical access to the chip (CC) takes place, the data groups (10, 20) each comprising an operation code (OC), the length of which is shorter in the second data group (20) than in the first data group (10), and each data group (10, 20) being identifiable by the bit pattern of the operation code (OC).