Abstract: Apparatus for monitoring and controlling the sequence analysis of processor operations in electronic digital computers. Each flip-flop in a flip-flop chain is associated with an operational step for setting up a monitoring and check sequence. The sequence is controlled by a flip-flop ring and consists of several steps each of which represents a monitoring or check function. An oscillator signal is fed to all flip-flop stages, together with a further control signal. Switching of flip-flops is effected in such a manner that at any one time only one flip-flop is on, its output signal and a coinciding oscillator signal generating a control signal which is converted in an address generator into an address for fetching a subroutine from a storage to control the monitoring and check function associated with the flip-flop.