Abstract: A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.

Abstract: A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

Abstract: A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.

Abstract: A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

Abstract: A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.

Abstract: A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.

Abstract: A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.

Abstract: An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.