Patents by Inventor Juergen Leib

Juergen Leib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10954591
    Abstract: The invention relates to a method for producing a structured coating on a substrate, wherein the method comprises the following steps: providing a substrate having a surface to be coated and producing a structured coating on the surface of the substrate to be coated by depositing at least one evaporation coating material, namely aluminium oxide, silicon dioxide, silicon nitride, or titanium dioxide, on the surface of the substrate to be coated by means of thermal evaporation of the at least one evaporation coating material and using additive structuring. The invention further relates to a coated substrate and a semi-finished product having a coated substrate.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: March 23, 2021
    Assignee: MSG LITHOGLAS AG
    Inventors: Jürgen Leib, Ulli Hansen, Simon Maus
  • Patent number: 10898136
    Abstract: A monitoring device for monitoring the well-being of animals, the monitoring device including a carrier arrangement which can be attached to an animal and which has at least one sensor for sensing a vital function of an animal wearing the carrier arrangement. In the event of a deviation of an actual state from a target state of the animal that leaves a tolerance range, an output signal signaling the deviation is outputted by an output unit.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: January 26, 2021
    Inventors: Juergen Leib, Michael Gruener
  • Publication number: 20170095206
    Abstract: A monitoring device for monitoring the well-being of animals, the monitoring device including a carrier arrangement which can be attached to an animal and which has at least one sensor for sensing a vital function of an animal wearing the carrier arrangement. In the event of a deviation of an actual state from a target state of the animal that leaves a tolerance range, an output signal signaling the deviation is outputted by an output unit.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Inventors: Juergen Leib, Michael Gruener
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: Jürgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8742588
    Abstract: The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion (11) of the via hole (9) and etching a second lengthwise portion (12) of the via hole (9); whereby the first lengthwise portion (11) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 3, 2014
    Assignee: ÅAC Microtec AB
    Inventors: Peter Nilsson, Jürgen Leib, Robert Thorslund
  • Patent number: 8659206
    Abstract: The invention relates to a method for producing a dielectric layer (3) in an electroacoustic component (1), in particular a component operating with acoustic surface waves or bulk acoustic waves, comprising a substrate and an associated electrode structure, in which the dielectric layer (3) is formed at least in part by depositing by a thermal vapor deposition process at least one evaporation material selected from the following group of layer vaporising materials: vapor deposition glass material such as borosilicate glass, silicon nitride and aluminum oxide. The invention further relates to an electroacoustic component.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: February 25, 2014
    Assignee: MSG Lithoglas AG
    Inventors: Ulli Hansen, Jürgen Leib, Simon Maus
  • Patent number: 8420445
    Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: April 16, 2013
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventor: Juergen Leib
  • Patent number: 8399293
    Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 19, 2013
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Juergen Leib, Hidefumi Yamamoto
  • Patent number: 8349707
    Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 8, 2013
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
  • Publication number: 20120314393
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Application
    Filed: September 24, 2010
    Publication date: December 13, 2012
    Applicant: MSG LITHOGLAS AG
    Inventors: Jürgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8324024
    Abstract: The invention relates to a method for production of packaged electronic, in particular optoelectronic, components in a composite wafer, in which the packaging is carried out by fitting microframe structures of a cover substrate composed of glass, and the composite wafer is broken up along trenches which are produced in the cover substrate, and to packaged electronic components which can be produced using this method, comprising a composite of a mount substrate and a cover substrate, with at least one functional element and at least one bonding element, which makes contact with the functional element, being arranged on the mount substrate, with the cover substrate being a microstructured glass which is arranged on the mount substrate, and forms a cavity above the functional element, and with the bonding elements being located outside the cavity.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: December 4, 2012
    Assignee: Schott AG
    Inventors: Juergen Leib, Dietrich Mund
  • Patent number: 8309384
    Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: November 13, 2012
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventor: Juergen Leib
  • Patent number: 8273671
    Abstract: A glass material for producing insulation layers is provided. The glass material can improve the radio-frequency properties of radio-frequency substrates or radio-frequency conductor arrangements. In one embodiment, the glass material for producing insulation layers for radio-frequency substrates or radio-frequency conductor arrangements is an applied layer with a layer thickness in the range between 0.05 ?m and 5?mm and has a loss factor tan ? of less than or equal to 70*10?4 in at least a frequency range above 1 GHz.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 25, 2012
    Assignee: Schott AG
    Inventors: Jürgen Leib, Dietrich Mund
  • Publication number: 20120231212
    Abstract: The invention relates to a method for producing a structured coating on a substrate, wherein the method comprises the following steps: providing a substrate having a surface to be coated and producing a structured coating on the surface of the substrate to be coated by depositing at least one evaporation coating material, namely aluminium oxide, silicon dioxide, silicon nitride, or titanium dioxide, on the surface of the substrate to be coated by means of thermal evaporation of the at least one evaporation coating material and using additive structuring. The invention further relates to a coated substrate and a semi-finished product having a coated substrate.
    Type: Application
    Filed: July 22, 2010
    Publication date: September 13, 2012
    Inventors: Jürgen Leib, Ulli Hansen, Simon Maus
  • Patent number: 8114304
    Abstract: In order to achieve an integration of functional structures into the housing of electronic components, provision is made of a method for producing an electronic component comprising at least one semiconductor element having at least one sensor-technologically active and/or emitting device on at least one side, the method comprising the following steps: provision of at least one die on a wafer, production of at least one patterned support having at least one structure which is functional for the sensor-technologically active and/or emitting device, joining together of the wafer with the at least one support, so that that side of the die which has the sensor-technologically active and/or emitting device faces the support, separation of the die.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: February 14, 2012
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Jürgen Leib, Florian Bieck
  • Publication number: 20120003791
    Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLC
    Inventors: Juergen Leib, Hidefumi Yamamoto
  • Patent number: 8017435
    Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: September 13, 2011
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Juergen Leib, Hidefumi Yamamoto
  • Publication number: 20110201197
    Abstract: The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion (1 1) of the via hole (9) and etching a second lengthwise portion (12) of the via hole (9); whereby the first lengthwise portion (11) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.
    Type: Application
    Filed: October 15, 2009
    Publication date: August 18, 2011
    Inventors: Peter Nilsson, Jürgen Leib, Robert Thorslund
  • Publication number: 20110175487
    Abstract: The invention relates to a method for producing a dielectric layer (3) in an electroacoustic component (1), in particular a component operating with acoustic surface waves or bulk acoustic waves, comprising a substrate and an associated electrode structure, in which the dielectric layer (3) is formed at least in part by depositing by a thermal vapour deposition process at least one evaporation material selected from the following group of layer vaporising materials: vapour deposition glass material such as borosilicate glass, silicon nitride and aluminium oxide. The invention further relates to an electroacoustic component.
    Type: Application
    Filed: July 23, 2009
    Publication date: July 21, 2011
    Inventors: Ulli Hansen, Jürgen Leib, Simon Maus
  • Patent number: 7880179
    Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: February 1, 2011
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Dipl.-Ing. Florian Bieck, Jürgen Leib