Patents by Inventor Juergen Pille

Juergen Pille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6785781
    Abstract: A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jens Leenstra, Juergen Pille, Rolf Sautter, Dieter Wendel
  • Patent number: 6725332
    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jens Leenstra, Antje Mueller, Juergen Pille, Dieter Wendel
  • Publication number: 20040027885
    Abstract: A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 12, 2004
    Applicant: International Business Machines Corporation
    Inventors: Stefan Buettner, Jens Leenstra, Juergen Pille, Christian Schweizer
  • Patent number: 6668341
    Abstract: Storage devices are presented which have some facility of error indication and error correction. The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted. The approach of doubling only the storing elements can be extended to implement a triple storing element (10, 12, 30) in the same cell. Then, with the help of a small and simple error correction logic (32) in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ulrich Krauch, Antje Mueller, Juergen Pille, Dieter Wendel
  • Publication number: 20030208672
    Abstract: A method and system for operating a high frequency outprocessor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no_dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed. Bypassing the pipeline stages for this “no dependency” conditions is especially important since a no dependency is found when the queue is empty. Furthermore, this bypass is very effective when the queue is relatively empty. Therefore, introducing such a bypass reduces effectively the performance drawback of a longer pipeline.
    Type: Application
    Filed: December 20, 2001
    Publication date: November 6, 2003
    Applicant: IBM
    Inventors: Jens Leenstra, Antje Mueller, Juergen Pille, Dieter Wendel
  • Patent number: 6629215
    Abstract: In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Rolf Sautter, Dieter Wendel, George M. Lattimore
  • Patent number: 6614265
    Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: September 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Stefan Buettner, Guenter Mayer, Juergen Pille, Dieter Wendel
  • Patent number: 6537861
    Abstract: An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Karl-Eugen Kroell, Juergen Pille, Helmut Schettler
  • Publication number: 20020149408
    Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.
    Type: Application
    Filed: December 5, 2001
    Publication date: October 17, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefan Buettner, Guenter Mayer, Juergen Pille, Dieter Wendel
  • Publication number: 20020016705
    Abstract: An improved hardware circuit simulation method in particular for history-dependent and cyclic operation-sensitive hardware circuits, like SOI-type hardware, checks for correct cyclic boundary conditions by performing a first run of a DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed before being simulated in vain with a great amount of work and computing time. A transient simulation can be appended for automated correction of dynamic errors.
    Type: Application
    Filed: July 10, 2001
    Publication date: February 7, 2002
    Applicant: International Business Machines Corporation
    Inventors: Karl-Eugen Kroell, Juergen Pille, Helmut Schettler
  • Patent number: 6341093
    Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: January 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Martin Eckert, Guenter Mayer, Juergen Pille, Dieter Wendel
  • Publication number: 20020003733
    Abstract: The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
    Type: Application
    Filed: June 1, 2001
    Publication date: January 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Martin Eckert, Guenter Mayer, Juergen Pille, Dieter Wendel
  • Publication number: 20010044882
    Abstract: In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 22, 2001
    Applicant: International Business Machines Corporation
    Inventors: Juergen Pille, Rolf Sautter, Dieter Wendel, George M. Lattimore
  • Publication number: 20010034817
    Abstract: A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.
    Type: Application
    Filed: April 3, 2001
    Publication date: October 25, 2001
    Applicant: International Business Machines Corporation
    Inventors: Jens Leenstra, Juergen Pille, Rolf Sautter, Dieter Wendel
  • Publication number: 20010029557
    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.
    Type: Application
    Filed: March 22, 2001
    Publication date: October 11, 2001
    Inventors: Jens Leenstra, Antje Mueller, Juergen Pille, Dieter Wendel
  • Patent number: 6295232
    Abstract: A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Klaus Helwig, Dieter Wendel
  • Publication number: 20010005331
    Abstract: A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).
    Type: Application
    Filed: December 8, 2000
    Publication date: June 28, 2001
    Inventors: Juergen Pille, Klaus Helwig, Dieter Wendel