Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.

Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.

Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.

Abstract: Verifying the functionality of an integrated circuit, the integrated circuit being operable for processing a data packet thereby generating a data processing result. A data packet to be processed is evaluated to determine if the data packet is an erroneous data packet. If the data packet is identified as an erroneous data packet, a modified data packet is generated by modifying the erroneous data packet and providing the modified data packet to the integrated circuit. A determination is made as to whether the data processing result comprises the modification; and a malfunction of the integrated circuit is signaled, if the data processing result comprises the modification.

Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.

Abstract: To assist verification of a digital circuit design, a data processing system presents, within a graphical user interface of a display device, a presentation including a plurality of verification notifications arising from verification of a digital circuit design. The data processing system detects one or more user operations by which a user interacts with the plurality of verification notifications utilizing one or more user input devices and stores, in a memory, user operation information regarding the one or more user operations detected by the data processing system. The data processing system determines, based on said user operation information, a recommended subsequent user operation and presents, within the graphical user interface, an indication of the recommended subsequent user operation.

Abstract: To assist verification of a digital circuit design, a data processing system presents, within a graphical user interface of a display device, a presentation including a plurality of verification notifications arising from verification of a digital circuit design. The data processing system detects one or more user operations by which a user interacts with the plurality of verification notifications utilizing one or more user input devices and stores, in a memory, user operation information regarding the one or more user operations detected by the data processing system. The data processing system determines, based on said user operation information, a recommended subsequent user operation and presents, within the graphical user interface, an indication of the recommended subsequent user operation.