Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.

Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.

Abstract: A data processing device is provided.

Abstract: The present invention relates to fusion molecules that have binding specificity for pyoverdine type I, II and III and pyochelin and can be used in various applications, including diagnostic and/or therapeutic applications, for example, to inhibit or reduce growth of P. aeruginosa and/or to prevent or treat P. aeruginosa biofilm infection as well as diseases or disorders associated with P. aeruginosa biofilm infection. The present invention also concerns methods of producing the fusion molecules described herein as well as compositions and kits comprising such fusion molecules. The present invention further relates to nucleic acid molecules encoding the fusion molecules described herein.

Abstract: A method for determining the dryness of a fibrous web, in particular a tissue web, during the production of the fibrous web, is carried out in a machine including a drying cylinder, in particular a Yankee cylinder, to which at least one, preferably two, dryer hoods are assigned, and a reel-up for winding up the fibrous web. The determination of the dryness of the fibrous web is carried out before the drying cylinder on the basis of measured values which describe the following variables: the amount of solids in the fiber web at the reel-up, the amount of water in the fiber web at the reel-up, and the amount of water which is evaporated in the dryer hood or hoods. A method for controlling or regulating a machine for producing a fibrous web, a computer program and computer program product are also provided.

Abstract: A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.

Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.

Abstract: In known methods for producing a glass component, a void-containing intermediate product containing doped or non-doped SiO2 is inserted into a sheath tube composed of glass, which has a longitudinal axis and an inner bore, and is thermally treated therein. In order to subject the intermediate product to a thermal and/or reactive treatment that is reproducible and uniform in its effect from this starting point, it is proposed in one embodiment that into the sheath tube's inner bore a first gas-permeable gas diffuser is inserted which is displaceable along the sheath tube's longitudinal axis and is pressed against the intermediate product during the thermal treatment.

Abstract: A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.

Abstract: The present invention relates to fusion molecules that have binding specificity for pyoverdine type I, II and III and pyochelin and can be used in various applications, including diagnostic and/or therapeutic applications, for example, to inhibit or reduce growth of P. aeruginosa and/or to prevent or treat P. aeruginosa biofilm infection as well as diseases or disorders associated with P. aeruginosa biofilm infection. The present invention also concerns methods of producing the fusion molecules described herein as well as compositions and kits comprising such fusion molecules. The present invention further relates to nucleic acid molecules encoding the fusion molecules described herein.

Abstract: The present invention relates to fusion molecules that have binding specificity for pyoverdine type I, II and III and pyochelin and can be used in various applications, including diagnostic and/or therapeutic applications, for example, to inhibit or reduce growth of P. aeruginosa and/or to prevent or treat P. aeruginosa biofilm infection as well as diseases or disorders associated with P. aeruginosa biofilm infection. The present invention also concerns methods of producing the fusion molecules described herein as well as compositions and kits comprising such fusion molecules. The present invention further relates to nucleic acid molecules encoding the fusion molecules described herein.

Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.

Abstract: An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.