Patents by Inventor Juergen Schuderer

Juergen Schuderer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12599012
    Abstract: A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 7, 2026
    Assignee: Hitachi Energy Ltd
    Inventors: Juergen Schuderer, Slavo Kicin, Fabian Mohn, Gernot Riedel
  • Patent number: 12575430
    Abstract: The invention relates to a power semiconductor module comprising a conductive base, a conductive top, and at least two power semiconductor devices arranged between the conductive base and the conductive top. The semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V. An insulating spacer layer is arranged on the power semiconductor devices and at least partially between the conductive base and the conductive top. At least two vertical connection elements pass from the power semiconductor devices through the spacer layer and conductively connect the conductive top with the power semiconductor devices. The spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 10, 2026
    Assignee: HITACHI ENERGY LTD
    Inventors: Juergen Schuderer, Chunlei Liu, Slavo Kicin, Giovanni Salvatore, Fabian Mohn
  • Patent number: 12512413
    Abstract: An electrical contact arrangement electrically contacts at least two power semiconductor devices, and comprises at least two bond wires and at least three electrical contacts, comprising an alternating current contact, a positive direct current contact, and a negative direct current contact. Each electrical contact comprises a ground potential part; contact part; and insulation part on the ground potential part. The contact part is provided on the insulation part. At least two electrical contacts are separated by a gap between the insulation parts and the gap between the contact parts of the separated electrical contacts. A bond wire connects a first power semiconductor device on a contact part of the positive direct current contact with a contact part of the alternating current contact. A bond wire connects a second power semiconductor device on the contact part of the alternating current contact with a contact part of the negative direct current contact.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 30, 2025
    Assignee: HITACHI ENERGY LTD
    Inventors: Juergen Schuderer, Fabian Mohn, Chunlei Liu, Joonas Puukko
  • Patent number: 12068174
    Abstract: In one embodiment a power semiconductor module includes a substrate having a first substrate side for carrying an electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side has a flat surface and is adapted for coming in contact with a cooler. A cooling area that is surrounded by a connecting area is located at the second substrate side. A first casing component of the cooler is connected to the second substrate side at the connecting area and a second casing component is connected to the first casing component such that a cooling channel for providing the cooling area with cooling fluid is provided between the first casing component and the second casing component. A cooling structure can be welded to the cooling area at the second substrate side.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 20, 2024
    Assignee: Hitachi Energy Ltd
    Inventors: Daniele Torresin, Fabian Mohn, Bruno Agostini, Thomas Gradinger, Juergen Schuderer
  • Patent number: 12068290
    Abstract: A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: August 20, 2024
    Assignee: Hitachi Energy Ltd
    Inventors: Arne Schroeder, Slavo Kicin, Fabian Mohn, Juergen Schuderer
  • Publication number: 20240030101
    Abstract: A power module includes a power semiconductor module having a semiconductor chip arranged on a substrate. A lead frame is arranged in electrical contact with the semiconductor chip. Abase plate includes cooling structures and micro channels that are connected to an inlet port and an outlet port. A bond layer connects the power semiconductor module and the base plate. A mold compound is arranged on the power semiconductor module, the bond layer and the base plate. The bond layer is encapsulated completely by the power semiconductor module, the base plate and the mold compound and the lead frame is arranged at least partially within the mold compound.
    Type: Application
    Filed: September 16, 2021
    Publication date: January 25, 2024
    Inventors: Niko Pavlicek, Didier Cottet, Thomas Gradinger, Chunlei Liu, Fabian Mohn, Giovanni Salvatore, Juergen Schuderer, Daniele Torresin, Felix Traub
  • Publication number: 20230343715
    Abstract: An electrical contact arrangement electrically contacts at least two power semiconductor devices, and comprises at least two bond wires and at least three electrical contacts, comprising an alternating current contact, a positive direct current contact, and a negative direct current contact. Each electrical contact comprises a ground potential part; contact part; and insulation part on the ground potential part. The contact part is provided on the insulation part. At least two electrical contacts are separated by a gap between the insulation parts and the gap between the contact parts of the separated electrical contacts. A bond wire connects a first power semiconductor device on a contact part of the positive direct current contact with a contact part of the alternating current contact. A bond wire connects a second power semiconductor device on the contact part of the alternating current contact with a contact part of the negative direct current contact.
    Type: Application
    Filed: November 23, 2021
    Publication date: October 26, 2023
    Inventors: Juergen SCHUDERER, Fabian MOHN, Chunlei LIU, Joonas PUUKKO
  • Publication number: 20230335472
    Abstract: The invention relates to a power semiconductor module comprising a conductive base, a conductive top, and at least two power semiconductor devices arranged between the conductive base and the conductive top. The semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V. An insulating spacer layer is arranged on the power semiconductor devices and at least partially between the conductive base and the conductive top. At least two vertical connection elements pass from the power semiconductor devices through the spacer layer and conductively connect the conductive top with the power semiconductor devices. The spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices.
    Type: Application
    Filed: September 23, 2021
    Publication date: October 19, 2023
    Inventors: Juergen SCHUDERER, Chunlei LIU, Slavo KICIN, Giovanni SALVATORE, Fabian MOHN
  • Publication number: 20230116118
    Abstract: A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.
    Type: Application
    Filed: January 28, 2021
    Publication date: April 13, 2023
    Inventors: Juergen Schuderer, Slavo Kicin, Fabian Mohn, Gernot Riedel
  • Publication number: 20230048878
    Abstract: A power semiconductor module includes a substrate with a metallization layer that is structured. A semiconductor chip having a first side bonded to the metallization layer. A metal clip, which is a strip of metal, has a first planar part bonded to a second side of the semiconductor chip opposite to the first side. The metal clip also has a second planar part bonded to the metallization layer. A mold encapsulation at least partially encloses the substrate and the metal clip. The mold encapsulation has a recess approaching towards the first planar part of the metal clip. The semiconductor chip is completely enclosed by the mold encapsulation, the substrate and the metal clip and the first planar part of the metal clip is at least partially exposed by the recess. A sensor is accommodated in the recess.
    Type: Application
    Filed: January 27, 2021
    Publication date: February 16, 2023
    Inventors: Juergen Schuderer, Niko Pavlicek, Chunlei Liu, Arne Schroeder, Gerd Schlottig
  • Patent number: 11562911
    Abstract: One embodiment provides a method of providing a power semiconductor module with a cooler. A power semiconductor module includes a substrate having a first substrate side for carrying at least one electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side is connected to a first baseplate side and the baseplate also includes a second baseplate side being located opposite to its first baseplate side and being adapted for coming in contact with the cooler. The cooler includes a first casing component and a second casing component. The baseplate side is equipped with a cooling area that is surrounded by a connecting area.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 24, 2023
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Daniele Torresin, Thomas Gradinger, Juergen Schuderer
  • Publication number: 20220254653
    Abstract: In one embodiment a power semiconductor module includes a substrate having a first substrate side for carrying an electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side has a flat surface and is adapted for coming in contact with a cooler. A cooling area that is surrounded by a connecting area is located at the second substrate side. A first casing component of the cooler is connected to the second substrate side at the connecting area and a second casing component is connected to the first casing component such that a cooling channel for providing the cooling area with cooling fluid is provided between the first casing component and the second casing component. A cooling structure can be welded to the cooling area at the second substrate side.
    Type: Application
    Filed: July 24, 2020
    Publication date: August 11, 2022
    Inventors: Daniele Torresin, Fabian Mohn, Bruno Agostini, Thomas Gradinger, Juergen Schuderer
  • Publication number: 20220254654
    Abstract: One embodiment provides a method of providing a power semiconductor module with a cooler. A power semiconductor module includes a substrate having a first substrate side for carrying at least one electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side is connected to a first baseplate side and the baseplate also includes a second baseplate side being located opposite to its first baseplate side and being adapted for coming in contact with the cooler. The cooler includes a first casing component and a second casing component. The baseplate side is equipped with a cooling area that is surrounded by a connecting area.
    Type: Application
    Filed: July 23, 2020
    Publication date: August 11, 2022
    Inventors: Daniele Torresin, Thomas Gradinger, Juergen Schuderer
  • Publication number: 20220238493
    Abstract: A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 28, 2022
    Inventors: Arne Schroeder, Slavo Kicin, Fabian Mohn, Juergen Schuderer
  • Patent number: 10872830
    Abstract: A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 22, 2020
    Assignee: ABB Schweiz AG
    Inventors: Chunlei Liu, Juergen Schuderer, Franziska Brem, Munaf Rahimo, Peter Karl Steimer, Franc Dugal
  • Patent number: 10636732
    Abstract: A power module comprises at least one power semiconductor device with an electrical top contact area on a top side; and a multi-layer circuit board with multiple electrically conducting layers which are separated by multiple electrically isolating layers, the electrically isolating layers being laminated together with the electrically conducting layers; wherein the multi-layer circuit board has at least one cavity, which is opened to a top side of the multi-layer circuit board, which cavity reaches through at least two electrically conducting layers; wherein the power semiconductor device is attached with a bottom side to a bottom of the cavity; and wherein the power semiconductor device is electrically connected to a top side of the multi-layer circuit board with a conducting member bonded to the top contact area and bonded to the top side of the multi-layer circuit board.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 28, 2020
    Assignee: ABB Schweiz AG
    Inventors: Fabian Mohn, Juergen Schuderer, Felix Traub
  • Patent number: 10546795
    Abstract: The present application relates to a power semiconductor device, including a substrate having a first side and a second side, the first side and the second side being located opposite to each other, wherein the first side includes a cathode and the second side includes an anode, wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side and the second side, the junction termination is coated by a passivating coating, the passivating coating including at least one material selected from the group consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 28, 2020
    Assignee: ABB Schweiz AG
    Inventors: Lise Donzel, Juergen Schuderer, Jagoda Dobrzynska, Jan Vobecky
  • Publication number: 20190355634
    Abstract: A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventors: Chunlei Liu, Juergen Schuderer, Franziska Brem, Munaf Rahimo, Peter Karl Steimer, Franc Dugal
  • Patent number: 10283454
    Abstract: The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor and at least one power semiconductor diode, wherein at least a first substrate is provided for carrying the power semiconductor transistor in a first plane, the first plane lying parallel to the plane of the substrate, wherein the power semiconductor diode is provided in a second plane, wherein the first plane is positioned between the substrate and the second plane in a direction normal to the first plane and wherein the first plane is spaced apart from the second plane in a direction normal to the first plane.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 7, 2019
    Assignee: ABB Schweiz AG
    Inventors: Felix Traub, Fabian Mohn, Juergen Schuderer, Daniel Kearney, Slavo Kicin
  • Patent number: 10283436
    Abstract: A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the fir
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: May 7, 2019
    Assignee: ABB Schweiz AG
    Inventors: Juergen Schuderer, Fabian Mohn, Didier Cottet, Felix Traub, Daniel Kearney