Patents by Inventor Juergen Serrer

Juergen Serrer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TEST INTERCONNECT WITH INTEGRATED LOOPBACKS
    Publication number: 20260016533
    Abstract: Test interconnect systems and methods are described. In one example, a test interconnect includes. A device under test (DUT) interface for connecting to a DUT; a load board interface for connecting to a load board; a circuitized component including an integrated loopback for self-test or self-communication of the DUT; and one or more conductive paths for connecting the DUT to the load board.
    Type: Application
    Filed: May 6, 2025
    Publication date: January 15, 2026
    Inventors: James HASTINGS, Nader Nasser ABAZARNIA, Quaid Joher FURNITUREWALA, Rolf NEUWEILER, Juergen SERRER, Joe XIAO
  • TEST INTERCONNECT WITH CONDUCTIVE PLANES AND COMPONENTS FOR POWER INTEGRITY AND THERMAL MANAGEMENT
    Publication number: 20260016501
    Abstract: Test interconnect systems and methods are described. In one example, a test interconnect includes a housing structure that houses at least a portion of one or more compressible probes. The test interconnect also includes a plate that retains the one or more compressible probes relative to a load board, and a circuit board with one or more conductive planes that provide a conductive path for a supply voltage for a device under test. The circuit board is positioned on a side of the housing structure relative to a device under test that is opposite the load board side.
    Type: Application
    Filed: September 11, 2024
    Publication date: January 15, 2026
    Inventors: James HASTINGS, Quaid Joher FURNITUREWALA, Rolf NEUWEILER, Juergen SERRER, Joe XIAO
  • Multi-stage data processor with signal repeater
    Patent number: 7921344
    Abstract: A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: April 5, 2011
    Assignee: Verigy (Singapore Pte. Ltd.
    Inventor: Juergen Serrer
  • Multi-Stage Data Processor With Signal Repeater
    Publication number: 20090282302
    Abstract: A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.
    Type: Application
    Filed: February 7, 2006
    Publication date: November 12, 2009
    Inventor: Juergen Serrer