Abstract: In various embodiments, a computer-implemented method for testing an interposer or silicon bridge comprises moving, by automated test equipment, a probe proximate to a first contact of a device under test (DUT), moving, by the automated test equipment, a second probe proximate to a second contact of the DUT, where the first contact and second contact are connected via a wire, driving, by the automated test equipment, the first probe with a first RF signal to induce a second RF signal in the wire, measuring, by the automated test equipment via the second probe, the second RF signal, and generating, by the automated test equipment, a test result based on at least the second RF signal.

Abstract: In various embodiments, a method comprises for maintaining a target environmental test condition during testing of a device under test (DUT), the method comprising: determining a first intensity level associated with a current block of test data, the first intensity level indicating an amount of resources needed to execute the current block of test data, determining an amount of an activity-modification technique based, at least in part, on the first intensity level, and executing the amount of the activity-modification technique for changing an activity level of the DUT.

Abstract: Test interconnect systems and methods are described. In one example, a test interconnect includes. A device under test (DUT) interface for connecting to a DUT; a load board interface for connecting to a load board; a circuitized component including an integrated loopback for self-test or self-communication of the DUT; and one or more conductive paths for connecting the DUT to the load board.

Abstract: Test interconnect systems and methods are described. In one example, a test interconnect includes a housing structure that houses at least a portion of one or more compressible probes. The test interconnect also includes a plate that retains the one or more compressible probes relative to a load board, and a circuit board with one or more conductive planes that provide a conductive path for a supply voltage for a device under test. The circuit board is positioned on a side of the housing structure relative to a device under test that is opposite the load board side.

Abstract: A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.

Abstract: A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.