Patents by Inventor Juergen Steinbrenner

Juergen Steinbrenner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347491
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10325803
    Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Kuenle, Gerhard Schmidt, Martin Sporn, Markus Kahn, Juergen Steinbrenner, Ravi Joshi
  • Publication number: 20180247820
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Keshav Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Publication number: 20180247857
    Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.
    Type: Application
    Filed: May 3, 2018
    Publication date: August 30, 2018
    Inventors: Matthias KUENLE, Gerhard SCHMIDT, Martin SPORN, Markus KAHN, Juergen STEINBRENNER, Ravi JOSHI
  • Publication number: 20180237292
    Abstract: A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Inventors: Markus Kahn, Anna-Katharina Kaiser, Soenke Pirk, Juergen Steinbrenner, Julia-Magdalena Straeussnigg
  • Patent number: 10049879
    Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Patent number: 10043750
    Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 7, 2018
    Assignee: Infineon Technologies AG
    Inventors: Ravi Joshi, Juergen Steinbrenner
  • Publication number: 20180211821
    Abstract: According to various embodiments, a wafer chuck may include at least one support region configured to support a wafer in a receiving area; a central cavity surrounded by the at least one support region configured to support the wafer only along an outer perimeter; and a boundary structure surrounding the receiving area configured to retain the wafer in the receiving area.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Rudolf Kogler, Juergen Steinbrenner, Wolfgang Dastel, Harald Huetter, Markus Kahn
  • Publication number: 20180182629
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 9984915
    Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Matthias Kuenle, Gerhard Schmidt, Martin Sporn, Markus Kahn, Juergen Steinbrenner, Ravi Joshi
  • Patent number: 9941111
    Abstract: According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Schmidt, Markus Kahn, Christian Maier, Philipp Koch, Juergen Steinbrenner
  • Publication number: 20180076036
    Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.
    Type: Application
    Filed: May 1, 2017
    Publication date: March 15, 2018
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Publication number: 20180012836
    Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 11, 2018
    Inventors: Ravi Joshi, Juergen Steinbrenner
  • Patent number: 9773736
    Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Juergen Steinbrenner, Christian Fachmann, Petra Fischer, Roman Roth
  • Publication number: 20170271268
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 21, 2017
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Patent number: 9768273
    Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
  • Patent number: 9728480
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 9704800
    Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 11, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ravi Joshi, Juergen Steinbrenner
  • Patent number: 9666482
    Abstract: A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Publication number: 20170110331
    Abstract: A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Georg Ehrentraut, Petra Fischer, Richard Gaisberger, Christoph Gruber, Martin Poelzl, Juergen Steinbrenner